From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org
Subject: [PATCH v4 08/16] target/arm: Swap argument order for VSHL during decode
Date: Wed, 13 May 2020 09:32:37 -0700 [thread overview]
Message-ID: <20200513163245.17915-9-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200513163245.17915-1-richard.henderson@linaro.org>
Rather than perform the argument swap during code generation,
perform it during decode. This means it doesn't have to be
special cased later, and we can share code with aarch64 code
generation. Hopefully the decode comment addresses any confusion
that might arise in between.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/neon-dp.decode | 17 +++++++++++++++--
target/arm/translate-neon.inc.c | 3 +--
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index ec3a92fe75..593f7fff03 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -65,8 +65,21 @@ VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0 .... @3same
VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
-VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same
-VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same
+# The _rev suffix indicates that Vn and Vm are reversed. This is
+# the case for shifts. In the Arm ARM these insns are documented
+# with the Vm and Vn fields in their usual places, but in the
+# assembly the operands are listed "backwards", ie in the order
+# Dd, Dm, Dn where other insns use Dd, Dn, Dm. For QEMU we choose
+# to consider Vm and Vn as being in different fields in the insn,
+# which allows us to avoid special-casing shifts in the trans_
+# function code. We would otherwise need to manually swap the operands
+# over to call Neon helper functions that are shared with AArch64,
+# which does not have this odd reversed-operand situation.
+@3same_rev .... ... . . . size:2 .... .... .... . q:1 . . .... \
+ &3same vn=%vm_dp vm=%vn_dp vd=%vd_dp
+
+VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same_rev
+VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same_rev
VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.inc.c
index aefeff498a..416302bcc7 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -692,8 +692,7 @@ static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
uint32_t rn_ofs, uint32_t rm_ofs, \
uint32_t oprsz, uint32_t maxsz) \
{ \
- /* Note the operation is vshl vd,vm,vn */ \
- tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, \
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, \
oprsz, maxsz, &OPARRAY[vece]); \
} \
DO_3SAME(INSN, gen_##INSN##_3s)
--
2.20.1
next prev parent reply other threads:[~2020-05-13 16:51 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-13 16:32 [PATCH v4 00/16] target/arm: partial vector cleanup Richard Henderson
2020-05-13 16:32 ` [PATCH v4 01/16] target/arm: Create gen_gvec_[us]sra Richard Henderson
2020-05-13 16:32 ` [PATCH v4 02/16] target/arm: Create gen_gvec_{u,s}{rshr,rsra} Richard Henderson
2020-05-13 16:32 ` [PATCH v4 03/16] target/arm: Create gen_gvec_{sri,sli} Richard Henderson
2020-05-13 16:32 ` [PATCH v4 04/16] target/arm: Remove unnecessary range check for VSHL Richard Henderson
2020-05-13 16:32 ` [PATCH v4 05/16] target/arm: Tidy handle_vec_simd_shri Richard Henderson
2020-05-13 16:32 ` [PATCH v4 06/16] target/arm: Create gen_gvec_{ceq,clt,cle,cgt,cge}0 Richard Henderson
2020-05-13 16:32 ` [PATCH v4 07/16] target/arm: Create gen_gvec_{mla,mls} Richard Henderson
2020-05-13 16:32 ` Richard Henderson [this message]
2020-05-13 16:32 ` [PATCH v4 09/16] target/arm: Create gen_gvec_{cmtst,ushl,sshl} Richard Henderson
2020-05-13 16:32 ` [PATCH v4 10/16] target/arm: Create gen_gvec_{uqadd, sqadd, uqsub, sqsub} Richard Henderson
2020-05-13 16:32 ` [PATCH v4 11/16] target/arm: Remove fp_status from helper_{recpe, rsqrte}_u32 Richard Henderson
2020-05-13 16:32 ` [PATCH v4 12/16] target/arm: Create gen_gvec_{qrdmla,qrdmls} Richard Henderson
2020-05-13 16:32 ` [PATCH v4 13/16] target/arm: Pass pointer to qc to qrdmla/qrdmls Richard Henderson
2020-05-13 16:32 ` [PATCH v4 14/16] target/arm: Clear tail in gvec_fmul_idx_*, gvec_fmla_idx_* Richard Henderson
2020-05-13 16:32 ` [PATCH v4 15/16] target/arm: Vectorize SABD/UABD Richard Henderson
2020-05-13 16:32 ` [PATCH v4 16/16] target/arm: Vectorize SABA/UABA Richard Henderson
2020-05-14 10:27 ` [PATCH v4 00/16] target/arm: partial vector cleanup Peter Maydell
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