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[79.179.68.225]) by smtp.gmail.com with ESMTPSA id 60sm4583208wrp.92.2020.05.14.08.16.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 May 2020 08:17:00 -0700 (PDT) Date: Thu, 14 May 2020 11:16:58 -0400 From: "Michael S. Tsirkin" To: qemu-devel@nongnu.org Subject: [PATCH] msix: allow qword MSI-X table accesses Message-ID: <20200514151648.877882-1-mst@redhat.com> MIME-Version: 1.0 X-Mailer: git-send-email 2.24.1.751.gd10ce2899c X-Mutt-Fcc: =sent X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=205.139.110.61; envelope-from=mst@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/05/13 22:25:42 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jusual@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" PCI spec says: For all accesses to MSI-X Table and MSI-X PBA fields, software must use aligned full DWORD or aligned full QWORD transactions; otherwise, the result is undefined. However, since MSI-X was converted to use memory API, QEMU started blocking qword transactions, only allowing DWORD ones. Guests do not seem to use QWORD accesses, but let's be spec compliant. Fixes: 95524ae8dc8f ("msix: convert to memory API") Signed-off-by: Michael S. Tsirkin --- hw/pci/msix.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/pci/msix.c b/hw/pci/msix.c index 29187898f2..e6a5559038 100644 --- a/hw/pci/msix.c +++ b/hw/pci/msix.c @@ -199,6 +199,9 @@ static const MemoryRegionOps msix_table_mmio_ops = { .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 4, + .max_access_size = 8, + }, + .impl = { .max_access_size = 4, }, }; @@ -227,6 +230,9 @@ static const MemoryRegionOps msix_pba_mmio_ops = { .endianness = DEVICE_LITTLE_ENDIAN, .valid = { .min_access_size = 4, + .max_access_size = 8, + }, + .impl = { .max_access_size = 4, }, }; -- MST