[PATCH 0/2] target/xtensa: fix simcall for newer hardware

[PATCH 0/2] target/xtensa: fix simcall for newer hardware

[Max Filippov]

Hello,

this series fixes simcall opcode behavior on the recent xtensa cores
making it nop rather than illegal instruction when semihosting is
disabled.

Max Filippov (2):
  target/xtensa: fetch HW version from configuration overlay
  target/xtensa: fix simcall for newer hardware

 target/xtensa/cpu.h          | 1 +
 target/xtensa/overlay_tool.h | 8 +++++---
 target/xtensa/translate.c    | 9 ++++++---
 3 files changed, 12 insertions(+), 6 deletions(-)

-- 
2.20.1

[PATCH 1/2] target/xtensa: fetch HW version from configuration overlay

[Max Filippov]

Xtensa architecture has features which behavior depends on hardware
version. Provide hardware version information to translators: add
XtensaConfig::hw_version and use XCHAL_HW_VERSION from configuration
overlay to initialize it.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 target/xtensa/cpu.h          | 1 +
 target/xtensa/overlay_tool.h | 8 +++++---
 2 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h
index 7a46dccbe11b..32749378bfc7 100644
--- a/target/xtensa/cpu.h
+++ b/target/xtensa/cpu.h
@@ -464,6 +464,7 @@ struct XtensaConfig {
     XtensaMemory sysrom;
     XtensaMemory sysram;
 
+    unsigned hw_version;
     uint32_t configid[2];
 
     void *isa_internal;
diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h
index cab532095c9e..a994e69b6e96 100644
--- a/target/xtensa/overlay_tool.h
+++ b/target/xtensa/overlay_tool.h
@@ -60,8 +60,9 @@
 #define XCHAL_RESET_VECTOR1_VADDR XCHAL_RESET_VECTOR_VADDR
 #endif
 
-#ifndef XCHAL_HW_MIN_VERSION
-#define XCHAL_HW_MIN_VERSION 0
+#ifndef XCHAL_HW_VERSION
+#define XCHAL_HW_VERSION (XCHAL_HW_VERSION_MAJOR * 100 \
+                          + XCHAL_HW_VERSION_MINOR)
 #endif
 
 #ifndef XCHAL_LOOP_BUFFER_SIZE
@@ -100,7 +101,7 @@
     XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
     XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
     XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
-    XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000) || \
+    XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \
                   XCHAL_HAVE_EXCLUSIVE), XTENSA_OPTION_ATOMCTL) | \
     XCHAL_OPTION(XCHAL_HAVE_DEPBITS, XTENSA_OPTION_DEPBITS) | \
     /* Interrupts and exceptions */ \
@@ -498,6 +499,7 @@
     }
 
 #define CONFIG_SECTION \
+    .hw_version = XCHAL_HW_VERSION, \
     .configid = { \
         XCHAL_HW_CONFIGID0, \
         XCHAL_HW_CONFIGID1, \
-- 
2.20.1

[PATCH 2/2] target/xtensa: fix simcall for newer hardware

[Max Filippov]

After Xtensa release RE.2 simcall opcode has become nop for the
hardware instead of illegal instruction.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
 target/xtensa/translate.c | 9 ++++++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 546d2fa2facf..4bc15252c8a5 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -2367,9 +2367,10 @@ static bool test_ill_simcall(DisasContext *dc, const OpcodeArg arg[],
 #ifdef CONFIG_USER_ONLY
     bool ill = true;
 #else
-    bool ill = !semihosting_enabled();
+    /* Between RE.2 and RE.3 simcall opcode's become nop for the hardware. */
+    bool ill = dc->config->hw_version <= 250002 && !semihosting_enabled();
 #endif
-    if (ill) {
+    if (ill || !semihosting_enabled()) {
         qemu_log_mask(LOG_GUEST_ERROR, "SIMCALL but semihosting is disabled\n");
     }
     return ill;
@@ -2379,7 +2380,9 @@ static void translate_simcall(DisasContext *dc, const OpcodeArg arg[],
                               const uint32_t par[])
 {
 #ifndef CONFIG_USER_ONLY
-    gen_helper_simcall(cpu_env);
+    if (semihosting_enabled()) {
+        gen_helper_simcall(cpu_env);
+    }
 #endif
 }
 
-- 
2.20.1