* [PATCH] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
@ 2020-05-18 14:30 Peter Maydell
2020-05-19 15:02 ` Richard Henderson
2020-05-21 17:05 ` Peter Maydell
0 siblings, 2 replies; 4+ messages in thread
From: Peter Maydell @ 2020-05-18 14:30 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Riku Voipio, Laurent Vivier
The Arm signal-handling code has some parts ifdeffed with a
TARGET_CONFIG_CPU_32, which is always defined. This is a leftover
from when this code's structure was based on the Linux kernel
signal handling code, where it was intended to support 26-bit
Arm CPUs. The kernel dropped its CONFIG_CPU_32 in kernel commit
4da8b8208eded0ba21e3 in 2009.
QEMU has never had 26-bit CPU support and is unlikely to ever
add it; we certainly aren't going to support 26-bit Linux
binaries via linux-user mode. The ifdef is just unhelpful
noise, so remove it entirely.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
Based-on: <20200518142801.20503-1-peter.maydell@linaro.org>
("[PATCH v2] target/arm: Allow user-mode code to write CPSR.E via MSR")
to avoid a textual conflict.
linux-user/arm/signal.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
index 698985a647e..f21d1535e4d 100644
--- a/linux-user/arm/signal.c
+++ b/linux-user/arm/signal.c
@@ -126,8 +126,6 @@ struct rt_sigframe_v2
abi_ulong retcode[4];
};
-#define TARGET_CONFIG_CPU_32 1
-
/*
* For ARM syscalls, we encode the syscall number into the instruction.
*/
@@ -187,9 +185,7 @@ setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/
__put_user(env->regs[13], &sc->arm_sp);
__put_user(env->regs[14], &sc->arm_lr);
__put_user(env->regs[15], &sc->arm_pc);
-#ifdef TARGET_CONFIG_CPU_32
__put_user(cpsr_read(env), &sc->arm_cpsr);
-#endif
__put_user(/* current->thread.trap_no */ 0, &sc->trap_no);
__put_user(/* current->thread.error_code */ 0, &sc->error_code);
@@ -549,11 +545,9 @@ restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)
__get_user(env->regs[13], &sc->arm_sp);
__get_user(env->regs[14], &sc->arm_lr);
__get_user(env->regs[15], &sc->arm_pc);
-#ifdef TARGET_CONFIG_CPU_32
__get_user(cpsr, &sc->arm_cpsr);
cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
arm_rebuild_hflags(env);
-#endif
err |= !valid_user_regs(env);
--
2.20.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
2020-05-18 14:30 [PATCH] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 Peter Maydell
@ 2020-05-19 15:02 ` Richard Henderson
2020-05-21 17:05 ` Peter Maydell
1 sibling, 0 replies; 4+ messages in thread
From: Richard Henderson @ 2020-05-19 15:02 UTC (permalink / raw)
To: Peter Maydell, qemu-arm, qemu-devel; +Cc: Riku Voipio, Laurent Vivier
On 5/18/20 7:30 AM, Peter Maydell wrote:
> The Arm signal-handling code has some parts ifdeffed with a
> TARGET_CONFIG_CPU_32, which is always defined. This is a leftover
> from when this code's structure was based on the Linux kernel
> signal handling code, where it was intended to support 26-bit
> Arm CPUs. The kernel dropped its CONFIG_CPU_32 in kernel commit
> 4da8b8208eded0ba21e3 in 2009.
>
> QEMU has never had 26-bit CPU support and is unlikely to ever
> add it; we certainly aren't going to support 26-bit Linux
> binaries via linux-user mode. The ifdef is just unhelpful
> noise, so remove it entirely.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> Based-on: <20200518142801.20503-1-peter.maydell@linaro.org>
> ("[PATCH v2] target/arm: Allow user-mode code to write CPSR.E via MSR")
> to avoid a textual conflict.
>
> linux-user/arm/signal.c | 6 ------
> 1 file changed, 6 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
2020-05-18 14:30 [PATCH] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 Peter Maydell
2020-05-19 15:02 ` Richard Henderson
@ 2020-05-21 17:05 ` Peter Maydell
1 sibling, 0 replies; 4+ messages in thread
From: Peter Maydell @ 2020-05-21 17:05 UTC (permalink / raw)
To: qemu-arm, QEMU Developers; +Cc: Riku Voipio, Laurent Vivier
On Mon, 18 May 2020 at 15:30, Peter Maydell <peter.maydell@linaro.org> wrote:
>
> The Arm signal-handling code has some parts ifdeffed with a
> TARGET_CONFIG_CPU_32, which is always defined. This is a leftover
> from when this code's structure was based on the Linux kernel
> signal handling code, where it was intended to support 26-bit
> Arm CPUs. The kernel dropped its CONFIG_CPU_32 in kernel commit
> 4da8b8208eded0ba21e3 in 2009.
>
> QEMU has never had 26-bit CPU support and is unlikely to ever
> add it; we certainly aren't going to support 26-bit Linux
> binaries via linux-user mode. The ifdef is just unhelpful
> noise, so remove it entirely.
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
Applied to target-arm.next, thanks.
-- PMM
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH 00/10] target/arm: Various v8.1M minor features
@ 2020-10-12 15:33 Peter Maydell
2020-10-12 15:33 ` [PATCH] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32 Peter Maydell
0 siblings, 1 reply; 4+ messages in thread
From: Peter Maydell @ 2020-10-12 15:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
This patchseries implements various minor v8.1M new features,
notably the branch-future and low-overhead-loop extensions.
(None of this will get enabled until we have enough to implement
a CPU model which has v8.1M, which will be the Cortex-M55, but
as usual we can get stuff into the tree gradually.)
Patch 1 is a decodetree fix suggested by Richard that is
necessary to avoid wrong-decode of the changes to t32.decode
by later patches.
thanks
-- PMM
Peter Maydell (10):
decodetree: Fix codegen for non-overlapping group inside overlapping
group
target/arm: Implement v8.1M NOCP handling
target/arm: Implement v8.1M conditional-select insns
target/arm: Make the t32 insn[25:23]=111 group non-overlapping
target/arm: Don't allow BLX imm for M-profile
target/arm: Implement v8.1M branch-future insns (as NOPs)
target/arm: Implement v8.1M low-overhead-loop instructions
target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension
target/arm: Fix writing to FPSCR.FZ16 on M-profile
target/arm/cpu.h | 7 ++
target/arm/m-nocp.decode | 10 ++-
target/arm/t32.decode | 50 +++++++----
target/arm/cpu.c | 34 ++++---
target/arm/translate.c | 157 +++++++++++++++++++++++++++++++++
target/arm/vfp_helper.c | 30 +++++--
scripts/decodetree.py | 2 +-
target/arm/translate-vfp.c.inc | 17 +++-
8 files changed, 268 insertions(+), 39 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] linux-user/arm/signal.c: Drop TARGET_CONFIG_CPU_32
2020-10-12 15:33 [PATCH 00/10] target/arm: Various v8.1M minor features Peter Maydell
@ 2020-10-12 15:33 ` Peter Maydell
0 siblings, 0 replies; 4+ messages in thread
From: Peter Maydell @ 2020-10-12 15:33 UTC (permalink / raw)
To: qemu-arm, qemu-devel; +Cc: Richard Henderson
The Arm signal-handling code has some parts ifdeffed with a
TARGET_CONFIG_CPU_32, which is always defined. This is a leftover
from when this code's structure was based on the Linux kernel
signal handling code, where it was intended to support 26-bit
Arm CPUs. The kernel dropped its CONFIG_CPU_32 in kernel commit
4da8b8208eded0ba21e3 in 2009.
QEMU has never had 26-bit CPU support and is unlikely to ever
add it; we certainly aren't going to support 26-bit Linux
binaries via linux-user mode. The ifdef is just unhelpful
noise, so remove it entirely.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
Based-on: <20200518142801.20503-1-peter.maydell@linaro.org>
("[PATCH v2] target/arm: Allow user-mode code to write CPSR.E via MSR")
to avoid a textual conflict.
linux-user/arm/signal.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c
index 698985a647e..f21d1535e4d 100644
--- a/linux-user/arm/signal.c
+++ b/linux-user/arm/signal.c
@@ -126,8 +126,6 @@ struct rt_sigframe_v2
abi_ulong retcode[4];
};
-#define TARGET_CONFIG_CPU_32 1
-
/*
* For ARM syscalls, we encode the syscall number into the instruction.
*/
@@ -187,9 +185,7 @@ setup_sigcontext(struct target_sigcontext *sc, /*struct _fpstate *fpstate,*/
__put_user(env->regs[13], &sc->arm_sp);
__put_user(env->regs[14], &sc->arm_lr);
__put_user(env->regs[15], &sc->arm_pc);
-#ifdef TARGET_CONFIG_CPU_32
__put_user(cpsr_read(env), &sc->arm_cpsr);
-#endif
__put_user(/* current->thread.trap_no */ 0, &sc->trap_no);
__put_user(/* current->thread.error_code */ 0, &sc->error_code);
@@ -549,11 +545,9 @@ restore_sigcontext(CPUARMState *env, struct target_sigcontext *sc)
__get_user(env->regs[13], &sc->arm_sp);
__get_user(env->regs[14], &sc->arm_lr);
__get_user(env->regs[15], &sc->arm_pc);
-#ifdef TARGET_CONFIG_CPU_32
__get_user(cpsr, &sc->arm_cpsr);
cpsr_write(env, cpsr, CPSR_USER | CPSR_EXEC, CPSRWriteByInstr);
arm_rebuild_hflags(env);
-#endif
err |= !valid_user_regs(env);
--
2.20.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
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