From: Eric Auger <eric.auger@redhat.com>
To: eric.auger.pro@gmail.com, eric.auger@redhat.com,
qemu-devel@nongnu.org, qemu-arm@nongnu.org,
peter.maydell@linaro.org, peterx@redhat.com
Cc: jean-philippe@linaro.org, robh@kernel.org, robin.murphy@arm.com,
mst@redhat.com, zhangfei.gao@foxmail.com,
shameerali.kolothum.thodi@huawei.com, will@kernel.org
Subject: [PATCH 5/9] hw/arm/smmuv3: Store the starting level in SMMUTransTableInfo
Date: Thu, 21 May 2020 11:10:55 +0200 [thread overview]
Message-ID: <20200521091059.9453-6-eric.auger@redhat.com> (raw)
In-Reply-To: <20200521091059.9453-1-eric.auger@redhat.com>
Compute the starting level on CD decoding and store it
into SMMUTransTableInfo. We will need this information
on IOTLB lookup so let's avoid to recompute it each time.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
---
include/hw/arm/smmu-common.h | 1 +
hw/arm/smmu-common.c | 2 +-
hw/arm/smmuv3.c | 8 ++++++--
hw/arm/trace-events | 2 +-
4 files changed, 9 insertions(+), 4 deletions(-)
diff --git a/include/hw/arm/smmu-common.h b/include/hw/arm/smmu-common.h
index f6ee78e16c..676e53c086 100644
--- a/include/hw/arm/smmu-common.h
+++ b/include/hw/arm/smmu-common.h
@@ -50,6 +50,7 @@ typedef struct SMMUTransTableInfo {
uint64_t ttb; /* TT base address */
uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/
uint8_t granule_sz; /* granule page shift */
+ uint8_t starting_level; /* starting level */
} SMMUTransTableInfo;
struct SMMUTLBEntry {
diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c
index aa88b62efb..c2ed8346fb 100644
--- a/hw/arm/smmu-common.c
+++ b/hw/arm/smmu-common.c
@@ -224,7 +224,7 @@ static int smmu_ptw_64(SMMUTransCfg *cfg,
granule_sz = tt->granule_sz;
stride = granule_sz - 3;
inputsize = 64 - tt->tsz;
- level = 4 - (inputsize - 4) / stride;
+ level = tt->starting_level;
indexmask = (1ULL << (inputsize - (stride * (4 - level)))) - 1;
baseaddr = extract64(tt->ttb, 0, 48);
baseaddr &= ~indexmask;
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index db74d27add..12d3e972d6 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -482,7 +482,7 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
/* decode data dependent on TT */
for (i = 0; i <= 1; i++) {
- int tg, tsz;
+ int tg, tsz, input_size, stride;
SMMUTransTableInfo *tt = &cfg->tt[i];
cfg->tt[i].disabled = CD_EPD(cd, i);
@@ -502,11 +502,15 @@ static int decode_cd(SMMUTransCfg *cfg, CD *cd, SMMUEventInfo *event)
}
tt->tsz = tsz;
+ input_size = 64 - tt->tsz;
+ stride = tt->granule_sz - 3;
tt->ttb = CD_TTB(cd, i);
if (tt->ttb & ~(MAKE_64BIT_MASK(0, cfg->oas))) {
goto bad_cd;
}
- trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb, tt->granule_sz);
+ tt->starting_level = 4 - (input_size - 4) / stride;
+ trace_smmuv3_decode_cd_tt(i, tt->tsz, tt->ttb,
+ tt->granule_sz, tt->starting_level);
}
event->record_trans_faults = CD_R(cd);
diff --git a/hw/arm/trace-events b/hw/arm/trace-events
index b808a1bfc1..7263b9c586 100644
--- a/hw/arm/trace-events
+++ b/hw/arm/trace-events
@@ -39,7 +39,7 @@ smmuv3_translate_abort(const char *n, uint16_t sid, uint64_t addr, bool is_write
smmuv3_translate_success(const char *n, uint16_t sid, uint64_t iova, uint64_t translated, int perm) "%s sid=%d iova=0x%"PRIx64" translated=0x%"PRIx64" perm=0x%x"
smmuv3_get_cd(uint64_t addr) "CD addr: 0x%"PRIx64
smmuv3_decode_cd(uint32_t oas) "oas=%d"
-smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d"
+smmuv3_decode_cd_tt(int i, uint32_t tsz, uint64_t ttb, uint32_t granule_sz, uint8_t starting_level) "TT[%d]:tsz:%d ttb:0x%"PRIx64" granule_sz:%d starting_level=%d"
smmuv3_cmdq_cfgi_ste(int streamid) "streamid =%d"
smmuv3_cmdq_cfgi_ste_range(int start, int end) "start=0x%d - end=0x%d"
smmuv3_cmdq_cfgi_cd(uint32_t sid) "streamid = %d"
--
2.20.1
next prev parent reply other threads:[~2020-05-21 9:14 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-21 9:10 [PATCH 0/9] SMMUv3.2 Range-based TLB Invalidation Support Eric Auger
2020-05-21 9:10 ` [PATCH 1/9] hw/arm/smmu-common: Factorize some code in smmu_ptw_64() Eric Auger
2020-05-21 9:10 ` [PATCH 2/9] hw/arm/smmu-common: Add IOTLB helpers Eric Auger
2020-05-21 9:10 ` [PATCH 3/9] hw/arm/smmu: Simplify the IOTLB key format Eric Auger
2020-05-21 9:10 ` [PATCH 4/9] hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value Eric Auger
2020-05-21 9:10 ` Eric Auger [this message]
2020-05-21 9:10 ` [PATCH 6/9] hw/arm/smmu-common: Manage IOTLB block entries Eric Auger
2020-05-21 9:10 ` [PATCH 7/9] hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper Eric Auger
2020-05-21 9:10 ` [PATCH 8/9] hw/arm/smmuv3: Get prepared for range invalidation Eric Auger
2020-05-21 9:10 ` [PATCH 9/9] hw/arm/smmuv3: Advertise SMMUv3.2 " Eric Auger
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