From: Adam Lackorzynski <adam@l4re.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: QEMU Developers <qemu-devel@nongnu.org>
Subject: Re: [PATCH] target/arm: Init GIC CPU IF regs for A15/A7
Date: Mon, 1 Jun 2020 15:01:35 +0200 [thread overview]
Message-ID: <20200601130135.GA284778@os.inf.tu-dresden.de> (raw)
In-Reply-To: <CAFEAcA--vg0iPZmHacGUxkF7tOP9iFeei4rSksQO_fFh3wjtMA@mail.gmail.com>
On Mon Jun 01, 2020 at 13:36:13 +0100, Peter Maydell wrote:
> On Sat, 30 May 2020 at 00:07, Adam Lackorzynski <adam@l4re.org> wrote:
> >
> > Initialize the CPU interface registers also
> > for Cortex-A15 and Cortex-A7 CPU models, in
> > the same way as done for 64bit CPU models.
> > This fixes usage of GICv3 in virtualization
> > contexts in 32bit configurations.
> >
> > Signed-off-by: Adam Lackorzynski <adam@l4re.org>
>
> Hi; I'm confused by this patch. The Cortex-A15 and Cortex-A7
> do not have or support the GICv3, so why would we need
> to set GICv3-specific settings for them?
>
> We're probably missing a sanity-check somewhere
> to forbid user attempts to use non-GICv3 CPUs with
> the GICv3.
Indeed that's another option. Besides that A15+GICv3 currently just
works with this.
So I guess the alternative is to switch to 32bit from EL3 when using an A57?
Thanks,
Adam
next prev parent reply other threads:[~2020-06-01 13:02 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-29 23:06 [PATCH] target/arm: Init GIC CPU IF regs for A15/A7 Adam Lackorzynski
2020-06-01 12:36 ` Peter Maydell
2020-06-01 13:01 ` Adam Lackorzynski [this message]
2020-06-01 13:17 ` Peter Maydell
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