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[83.51.162.43]) by smtp.gmail.com with ESMTPSA id u12sm6824954wrq.90.2020.06.01.07.29.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 01 Jun 2020 07:29:32 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2 0/8] hw: Fix some incomplete memory region size Date: Mon, 1 Jun 2020 16:29:22 +0200 Message-Id: <20200601142930.29408-1-f4bug@amsat.org> X-Mailer: git-send-email 2.21.3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x32d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Stefano Stabellini , Eduardo Habkost , "Michael S. Tsirkin" , Andrew Jeffery , Helge Deller , Paul Durrant , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , qemu-trivial@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Joel Stanley , Paolo Bonzini , Anthony Perard , xen-devel@lists.xenproject.org, Richard Henderson , qemu-ppc@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Series fully reviewed. Since v1: - Add parenthesis on the Xen patch (Paul Durrant) - Add Peter's R-b tags memory_region_set_size() handle the 16 Exabytes limit by special-casing the UINT64_MAX value. This is not a problem for the 32-bit maximum, 4 GiB, but in some places we incorrectly use UINT32_MAX instead of 4 GiB, and end up missing 1 byte in the memory region. This series fixes the cases I encountered. Also included few patches while reviewing, I replaced some magic values by the IEC binary prefix equivalent. Regards, Phil. Philippe Mathieu-Daudé (8): hw/arm/aspeed: Correct DRAM container region size hw/pci-host/prep: Correct RAVEN bus bridge memory region size hw/pci/pci_bridge: Correct pci_bridge_io memory region size hw/pci/pci_bridge: Use the IEC binary prefix definitions hw/pci-host: Use the IEC binary prefix definitions hw/hppa/dino: Use the IEC binary prefix definitions hw/i386/xen/xen-hvm: Use the IEC binary prefix definitions target/i386/cpu: Use the IEC binary prefix definitions hw/arm/aspeed.c | 2 +- hw/hppa/dino.c | 4 ++-- hw/i386/xen/xen-hvm.c | 3 ++- hw/pci-host/i440fx.c | 3 ++- hw/pci-host/prep.c | 2 +- hw/pci-host/q35.c | 2 +- hw/pci-host/versatile.c | 5 +++-- hw/pci/pci_bridge.c | 7 ++++--- target/i386/cpu.c | 2 +- 9 files changed, 17 insertions(+), 13 deletions(-) -- 2.21.3