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Tsirkin" To: Peter Maydell Subject: Re: [PATCH v2 2/2] pci: ensure configuration access is within bounds Message-ID: <20200604053351-mutt-send-email-mst@kernel.org> References: <20200603202251.1199170-1-ppandit@redhat.com> <20200603202251.1199170-3-ppandit@redhat.com> MIME-Version: 1.0 In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=207.211.31.120; envelope-from=mst@redhat.com; helo=us-smtp-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/04 01:14:08 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel P =?iso-8859-1?Q?=2E_Berrang=E9?= , Prasad J Pandit , Yi Ren , QEMU Developers , P J P , Gerd Hoffmann , Ren Ding , Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Hanqing Zhao Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Jun 04, 2020 at 10:10:07AM +0100, Peter Maydell wrote: > On Wed, 3 Jun 2020 at 21:26, P J P wrote: > > > > From: Prasad J Pandit > > > > While reading PCI configuration bytes, a guest may send an > > address towards the end of the configuration space. It may lead > > to an OOB access issue. Assert that 'address + len' is within > > PCI configuration space. > > What does the spec say should happen when the guest does this? Spec says anything can happen *to the device*. Naturally there's an expectation that while device might crash it stays resettable and does not blow up. > Does it depend on the pci controller implementation? > > thanks > -- PMM Shouldn't I think. -- MST