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Tsirkin" To: P J P Subject: Re: [PATCH v3] ati-vga: check address before reading configuration bytes (CVE-2020-13791) Message-ID: <20200604074539-mutt-send-email-mst@kernel.org> References: <20200604105524.46158-1-ppandit@redhat.com> MIME-Version: 1.0 In-Reply-To: <20200604105524.46158-1-ppandit@redhat.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=205.139.110.61; envelope-from=mst@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/04 01:08:38 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel P =?iso-8859-1?Q?=2E_Berrang=E9?= , Prasad J Pandit , Yi Ren , QEMU Developers , Gerd Hoffmann , Ren Ding , pbonzini@redhat.com, Philippe =?iso-8859-1?Q?Mathieu-Daud=E9?= , Hanqing Zhao Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Jun 04, 2020 at 04:25:24PM +0530, P J P wrote: > From: Prasad J Pandit > > While reading PCI configuration bytes, a guest may send an > address towards the end of the configuration space. It may lead > to an OOB access issue. Add check to ensure 'address + size' is > within PCI configuration space. > > Reported-by: Ren Ding > Reported-by: Hanqing Zhao > Reported-by: Yi Ren > Suggested-by: BALATON Zoltan > Signed-off-by: Prasad J Pandit BTW, this only happens on unaligned accesses. And the IO memory region in question does not set valid.unaligned or .impl.unaligned. And the documentation says: - .valid.unaligned specifies that the *device being modelled* supports unaligned accesses; if false, unaligned accesses will invoke the appropriate bus or CPU specific behaviour. and - .impl.unaligned specifies that the *implementation* supports unaligned accesses; if false, unaligned accesses will be emulated by two aligned accesses. Is this then another case of a memory core bug which should have either failed the access or split it? > --- > hw/display/ati.c | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > Update v3: avoid modifying 'addr' variable > -> https://lists.gnu.org/archive/html/qemu-devel/2020-06/msg00834.html > > diff --git a/hw/display/ati.c b/hw/display/ati.c > index 67604e68de..b4d0fd88b7 100644 > --- a/hw/display/ati.c > +++ b/hw/display/ati.c > @@ -387,7 +387,9 @@ static uint64_t ati_mm_read(void *opaque, hwaddr addr, unsigned int size) > val = s->regs.crtc_pitch; > break; > case 0xf00 ... 0xfff: > - val = pci_default_read_config(&s->dev, addr - 0xf00, size); > + if ((addr - 0xf00) + size <= pci_config_size(&s->dev)) { > + val = pci_default_read_config(&s->dev, addr - 0xf00, size); > + } > break; > case CUR_OFFSET: > val = s->regs.cur_offset; > -- > 2.26.2