From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com,
wenmeng_zhang@c-sky.com,
Alistair Francis <alistair.francis@wdc.com>,
palmer@dabbelt.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v9 18/61] target/riscv: vector single-width integer multiply instructions
Date: Wed, 10 Jun 2020 19:37:05 +0800 [thread overview]
Message-ID: <20200610113748.4754-19-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200610113748.4754-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/helper.h | 33 +++++
target/riscv/insn32.decode | 8 ++
target/riscv/insn_trans/trans_rvv.inc.c | 10 ++
target/riscv/vector_helper.c | 163 ++++++++++++++++++++++++
4 files changed, 214 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 32f4c76b34..08c1c02e13 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -529,3 +529,36 @@ DEF_HELPER_6(vmax_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vmax_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vmax_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vmax_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vmul_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmul_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmul_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmul_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulh_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulh_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulh_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulh_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vmul_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmul_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmul_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmul_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulh_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulh_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulh_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulh_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vmulhsu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index aafbdc6be7..abfed469bc 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -363,6 +363,14 @@ vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm
vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm
vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm
vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm
+vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm
+vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm
+vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm
+vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm
+vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm
+vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm
+vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm
+vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index cbcb40e682..de5b8b7df6 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1571,3 +1571,13 @@ GEN_OPIVX_TRANS(vminu_vx, opivx_check)
GEN_OPIVX_TRANS(vmin_vx, opivx_check)
GEN_OPIVX_TRANS(vmaxu_vx, opivx_check)
GEN_OPIVX_TRANS(vmax_vx, opivx_check)
+
+/* Vector Single-Width Integer Multiply Instructions */
+GEN_OPIVV_GVEC_TRANS(vmul_vv, mul)
+GEN_OPIVV_TRANS(vmulh_vv, opivv_check)
+GEN_OPIVV_TRANS(vmulhu_vv, opivv_check)
+GEN_OPIVV_TRANS(vmulhsu_vv, opivv_check)
+GEN_OPIVX_GVEC_TRANS(vmul_vx, muls)
+GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
+GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
+GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index cb41daa3ac..3319370ae2 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -859,6 +859,10 @@ GEN_VEXT_AMO(vamomaxuw_v_w, uint32_t, uint32_t, idx_w, clearl)
#define OP_UUU_H uint16_t, uint16_t, uint16_t, uint16_t, uint16_t
#define OP_UUU_W uint32_t, uint32_t, uint32_t, uint32_t, uint32_t
#define OP_UUU_D uint64_t, uint64_t, uint64_t, uint64_t, uint64_t
+#define OP_SUS_B int8_t, uint8_t, int8_t, uint8_t, int8_t
+#define OP_SUS_H int16_t, uint16_t, int16_t, uint16_t, int16_t
+#define OP_SUS_W int32_t, uint32_t, int32_t, uint32_t, int32_t
+#define OP_SUS_D int64_t, uint64_t, int64_t, uint64_t, int64_t
/* operation of two vector elements */
typedef void opivv2_fn(void *vd, void *vs1, void *vs2, int i);
@@ -1603,3 +1607,162 @@ GEN_VEXT_VX(vmax_vx_b, 1, 1, clearb)
GEN_VEXT_VX(vmax_vx_h, 2, 2, clearh)
GEN_VEXT_VX(vmax_vx_w, 4, 4, clearl)
GEN_VEXT_VX(vmax_vx_d, 8, 8, clearq)
+
+/* Vector Single-Width Integer Multiply Instructions */
+#define DO_MUL(N, M) (N * M)
+RVVCALL(OPIVV2, vmul_vv_b, OP_SSS_B, H1, H1, H1, DO_MUL)
+RVVCALL(OPIVV2, vmul_vv_h, OP_SSS_H, H2, H2, H2, DO_MUL)
+RVVCALL(OPIVV2, vmul_vv_w, OP_SSS_W, H4, H4, H4, DO_MUL)
+RVVCALL(OPIVV2, vmul_vv_d, OP_SSS_D, H8, H8, H8, DO_MUL)
+GEN_VEXT_VV(vmul_vv_b, 1, 1, clearb)
+GEN_VEXT_VV(vmul_vv_h, 2, 2, clearh)
+GEN_VEXT_VV(vmul_vv_w, 4, 4, clearl)
+GEN_VEXT_VV(vmul_vv_d, 8, 8, clearq)
+
+static int8_t do_mulh_b(int8_t s2, int8_t s1)
+{
+ return (int16_t)s2 * (int16_t)s1 >> 8;
+}
+
+static int16_t do_mulh_h(int16_t s2, int16_t s1)
+{
+ return (int32_t)s2 * (int32_t)s1 >> 16;
+}
+
+static int32_t do_mulh_w(int32_t s2, int32_t s1)
+{
+ return (int64_t)s2 * (int64_t)s1 >> 32;
+}
+
+static int64_t do_mulh_d(int64_t s2, int64_t s1)
+{
+ uint64_t hi_64, lo_64;
+
+ muls64(&lo_64, &hi_64, s1, s2);
+ return hi_64;
+}
+
+static uint8_t do_mulhu_b(uint8_t s2, uint8_t s1)
+{
+ return (uint16_t)s2 * (uint16_t)s1 >> 8;
+}
+
+static uint16_t do_mulhu_h(uint16_t s2, uint16_t s1)
+{
+ return (uint32_t)s2 * (uint32_t)s1 >> 16;
+}
+
+static uint32_t do_mulhu_w(uint32_t s2, uint32_t s1)
+{
+ return (uint64_t)s2 * (uint64_t)s1 >> 32;
+}
+
+static uint64_t do_mulhu_d(uint64_t s2, uint64_t s1)
+{
+ uint64_t hi_64, lo_64;
+
+ mulu64(&lo_64, &hi_64, s2, s1);
+ return hi_64;
+}
+
+static int8_t do_mulhsu_b(int8_t s2, uint8_t s1)
+{
+ return (int16_t)s2 * (uint16_t)s1 >> 8;
+}
+
+static int16_t do_mulhsu_h(int16_t s2, uint16_t s1)
+{
+ return (int32_t)s2 * (uint32_t)s1 >> 16;
+}
+
+static int32_t do_mulhsu_w(int32_t s2, uint32_t s1)
+{
+ return (int64_t)s2 * (uint64_t)s1 >> 32;
+}
+
+/*
+ * Let A = signed operand,
+ * B = unsigned operand
+ * P = mulu64(A, B), unsigned product
+ *
+ * LET X = 2 ** 64 - A, 2's complement of A
+ * SP = signed product
+ * THEN
+ * IF A < 0
+ * SP = -X * B
+ * = -(2 ** 64 - A) * B
+ * = A * B - 2 ** 64 * B
+ * = P - 2 ** 64 * B
+ * ELSE
+ * SP = P
+ * THEN
+ * HI_P -= (A < 0 ? B : 0）
+ */
+
+static int64_t do_mulhsu_d(int64_t s2, uint64_t s1)
+{
+ uint64_t hi_64, lo_64;
+
+ mulu64(&lo_64, &hi_64, s2, s1);
+
+ hi_64 -= s2 < 0 ? s1 : 0;
+ return hi_64;
+}
+
+RVVCALL(OPIVV2, vmulh_vv_b, OP_SSS_B, H1, H1, H1, do_mulh_b)
+RVVCALL(OPIVV2, vmulh_vv_h, OP_SSS_H, H2, H2, H2, do_mulh_h)
+RVVCALL(OPIVV2, vmulh_vv_w, OP_SSS_W, H4, H4, H4, do_mulh_w)
+RVVCALL(OPIVV2, vmulh_vv_d, OP_SSS_D, H8, H8, H8, do_mulh_d)
+RVVCALL(OPIVV2, vmulhu_vv_b, OP_UUU_B, H1, H1, H1, do_mulhu_b)
+RVVCALL(OPIVV2, vmulhu_vv_h, OP_UUU_H, H2, H2, H2, do_mulhu_h)
+RVVCALL(OPIVV2, vmulhu_vv_w, OP_UUU_W, H4, H4, H4, do_mulhu_w)
+RVVCALL(OPIVV2, vmulhu_vv_d, OP_UUU_D, H8, H8, H8, do_mulhu_d)
+RVVCALL(OPIVV2, vmulhsu_vv_b, OP_SUS_B, H1, H1, H1, do_mulhsu_b)
+RVVCALL(OPIVV2, vmulhsu_vv_h, OP_SUS_H, H2, H2, H2, do_mulhsu_h)
+RVVCALL(OPIVV2, vmulhsu_vv_w, OP_SUS_W, H4, H4, H4, do_mulhsu_w)
+RVVCALL(OPIVV2, vmulhsu_vv_d, OP_SUS_D, H8, H8, H8, do_mulhsu_d)
+GEN_VEXT_VV(vmulh_vv_b, 1, 1, clearb)
+GEN_VEXT_VV(vmulh_vv_h, 2, 2, clearh)
+GEN_VEXT_VV(vmulh_vv_w, 4, 4, clearl)
+GEN_VEXT_VV(vmulh_vv_d, 8, 8, clearq)
+GEN_VEXT_VV(vmulhu_vv_b, 1, 1, clearb)
+GEN_VEXT_VV(vmulhu_vv_h, 2, 2, clearh)
+GEN_VEXT_VV(vmulhu_vv_w, 4, 4, clearl)
+GEN_VEXT_VV(vmulhu_vv_d, 8, 8, clearq)
+GEN_VEXT_VV(vmulhsu_vv_b, 1, 1, clearb)
+GEN_VEXT_VV(vmulhsu_vv_h, 2, 2, clearh)
+GEN_VEXT_VV(vmulhsu_vv_w, 4, 4, clearl)
+GEN_VEXT_VV(vmulhsu_vv_d, 8, 8, clearq)
+
+RVVCALL(OPIVX2, vmul_vx_b, OP_SSS_B, H1, H1, DO_MUL)
+RVVCALL(OPIVX2, vmul_vx_h, OP_SSS_H, H2, H2, DO_MUL)
+RVVCALL(OPIVX2, vmul_vx_w, OP_SSS_W, H4, H4, DO_MUL)
+RVVCALL(OPIVX2, vmul_vx_d, OP_SSS_D, H8, H8, DO_MUL)
+RVVCALL(OPIVX2, vmulh_vx_b, OP_SSS_B, H1, H1, do_mulh_b)
+RVVCALL(OPIVX2, vmulh_vx_h, OP_SSS_H, H2, H2, do_mulh_h)
+RVVCALL(OPIVX2, vmulh_vx_w, OP_SSS_W, H4, H4, do_mulh_w)
+RVVCALL(OPIVX2, vmulh_vx_d, OP_SSS_D, H8, H8, do_mulh_d)
+RVVCALL(OPIVX2, vmulhu_vx_b, OP_UUU_B, H1, H1, do_mulhu_b)
+RVVCALL(OPIVX2, vmulhu_vx_h, OP_UUU_H, H2, H2, do_mulhu_h)
+RVVCALL(OPIVX2, vmulhu_vx_w, OP_UUU_W, H4, H4, do_mulhu_w)
+RVVCALL(OPIVX2, vmulhu_vx_d, OP_UUU_D, H8, H8, do_mulhu_d)
+RVVCALL(OPIVX2, vmulhsu_vx_b, OP_SUS_B, H1, H1, do_mulhsu_b)
+RVVCALL(OPIVX2, vmulhsu_vx_h, OP_SUS_H, H2, H2, do_mulhsu_h)
+RVVCALL(OPIVX2, vmulhsu_vx_w, OP_SUS_W, H4, H4, do_mulhsu_w)
+RVVCALL(OPIVX2, vmulhsu_vx_d, OP_SUS_D, H8, H8, do_mulhsu_d)
+GEN_VEXT_VX(vmul_vx_b, 1, 1, clearb)
+GEN_VEXT_VX(vmul_vx_h, 2, 2, clearh)
+GEN_VEXT_VX(vmul_vx_w, 4, 4, clearl)
+GEN_VEXT_VX(vmul_vx_d, 8, 8, clearq)
+GEN_VEXT_VX(vmulh_vx_b, 1, 1, clearb)
+GEN_VEXT_VX(vmulh_vx_h, 2, 2, clearh)
+GEN_VEXT_VX(vmulh_vx_w, 4, 4, clearl)
+GEN_VEXT_VX(vmulh_vx_d, 8, 8, clearq)
+GEN_VEXT_VX(vmulhu_vx_b, 1, 1, clearb)
+GEN_VEXT_VX(vmulhu_vx_h, 2, 2, clearh)
+GEN_VEXT_VX(vmulhu_vx_w, 4, 4, clearl)
+GEN_VEXT_VX(vmulhu_vx_d, 8, 8, clearq)
+GEN_VEXT_VX(vmulhsu_vx_b, 1, 1, clearb)
+GEN_VEXT_VX(vmulhsu_vx_h, 2, 2, clearh)
+GEN_VEXT_VX(vmulhsu_vx_w, 4, 4, clearl)
+GEN_VEXT_VX(vmulhsu_vx_d, 8, 8, clearq)
--
2.23.0
next prev parent reply other threads:[~2020-06-10 12:32 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-10 11:36 [PATCH v9 00/61] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 01/61] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 02/61] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 03/61] target/riscv: support vector extension csr LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 04/61] target/riscv: add vector configure instruction LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 05/61] target/riscv: add an internals.h header LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 06/61] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 07/61] target/riscv: add vector index " LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 08/61] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 09/61] target/riscv: add vector amo operations LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 10/61] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 11/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 13/61] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 14/61] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 15/61] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 16/61] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 17/61] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-06-10 11:37 ` LIU Zhiwei [this message]
2020-06-10 11:37 ` [PATCH v9 19/61] target/riscv: vector integer divide instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 20/61] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 21/61] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 22/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 23/61] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 24/61] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 25/61] target/riscv: vector single-width averaging " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 27/61] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 28/61] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 29/61] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 30/61] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 31/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 32/61] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 33/61] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 35/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 36/61] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 37/61] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 38/61] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 39/61] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-06-10 17:33 ` Richard Henderson
2020-06-11 1:11 ` LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 40/61] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 41/61] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 42/61] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 43/61] target/riscv: widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 44/61] target/riscv: narrowing " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 45/61] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 46/61] target/riscv: vector wideing " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 47/61] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 48/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 49/61] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 50/61] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 51/61] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 52/61] target/riscv: set-X-first " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 53/61] target/riscv: vector iota instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 54/61] target/riscv: vector element index instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 55/61] target/riscv: integer extract instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 56/61] target/riscv: integer scalar move instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 57/61] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-06-20 0:44 ` Alistair Francis
2020-06-20 1:09 ` LIU Zhiwei
2020-06-20 1:06 ` Alistair Francis
2020-06-20 1:40 ` LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 58/61] target/riscv: vector slide instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 59/61] target/riscv: vector register gather instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 60/61] target/riscv: vector compress instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 61/61] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
2020-06-10 15:37 ` [PATCH v9 00/61] target/riscv: support vector extension v0.7.1 no-reply
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