From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com,
wenmeng_zhang@c-sky.com,
Alistair Francis <alistair.francis@wdc.com>,
palmer@dabbelt.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v9 38/61] target/riscv: vector floating-point sign-injection instructions
Date: Wed, 10 Jun 2020 19:37:25 +0800 [thread overview]
Message-ID: <20200610113748.4754-39-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200610113748.4754-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 19 ++++++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 8 +++
target/riscv/vector_helper.c | 85 +++++++++++++++++++++++++
4 files changed, 118 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 12d959ba0d..d6e7ce57be 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -934,3 +934,22 @@ DEF_HELPER_6(vfmin_vf_d, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfmax_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfmax_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfmax_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_6(vfsgnj_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnj_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnj_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnjn_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnjn_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnjn_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnjx_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnjx_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnjx_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfsgnj_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnj_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnj_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnjn_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnjn_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnjn_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnjx_vf_h, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnjx_vf_w, void, ptr, ptr, i64, ptr, env, i32)
+DEF_HELPER_6(vfsgnjx_vf_d, void, ptr, ptr, i64, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 5ec5595e2c..ce2f497ed2 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -494,6 +494,12 @@ vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm
+vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm
+vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm
+vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm
+vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm
+vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm
+vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 0c1e45123d..6170fce05d 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2138,3 +2138,11 @@ GEN_OPFVV_TRANS(vfmin_vv, opfvv_check)
GEN_OPFVV_TRANS(vfmax_vv, opfvv_check)
GEN_OPFVF_TRANS(vfmin_vf, opfvf_check)
GEN_OPFVF_TRANS(vfmax_vf, opfvf_check)
+
+/* Vector Floating-Point Sign-Injection Instructions */
+GEN_OPFVV_TRANS(vfsgnj_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfsgnjn_vv, opfvv_check)
+GEN_OPFVV_TRANS(vfsgnjx_vv, opfvv_check)
+GEN_OPFVF_TRANS(vfsgnj_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfsgnjn_vf, opfvf_check)
+GEN_OPFVF_TRANS(vfsgnjx_vf, opfvf_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 82e570da4e..7a1c5311bb 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3844,3 +3844,88 @@ RVVCALL(OPFVF2, vfmax_vf_d, OP_UUU_D, H8, H8, float64_maxnum)
GEN_VEXT_VF(vfmax_vf_h, 2, 2, clearh)
GEN_VEXT_VF(vfmax_vf_w, 4, 4, clearl)
GEN_VEXT_VF(vfmax_vf_d, 8, 8, clearq)
+
+/* Vector Floating-Point Sign-Injection Instructions */
+static uint16_t fsgnj16(uint16_t a, uint16_t b, float_status *s)
+{
+ return deposit64(b, 0, 15, a);
+}
+
+static uint32_t fsgnj32(uint32_t a, uint32_t b, float_status *s)
+{
+ return deposit64(b, 0, 31, a);
+}
+
+static uint64_t fsgnj64(uint64_t a, uint64_t b, float_status *s)
+{
+ return deposit64(b, 0, 63, a);
+}
+
+RVVCALL(OPFVV2, vfsgnj_vv_h, OP_UUU_H, H2, H2, H2, fsgnj16)
+RVVCALL(OPFVV2, vfsgnj_vv_w, OP_UUU_W, H4, H4, H4, fsgnj32)
+RVVCALL(OPFVV2, vfsgnj_vv_d, OP_UUU_D, H8, H8, H8, fsgnj64)
+GEN_VEXT_VV_ENV(vfsgnj_vv_h, 2, 2, clearh)
+GEN_VEXT_VV_ENV(vfsgnj_vv_w, 4, 4, clearl)
+GEN_VEXT_VV_ENV(vfsgnj_vv_d, 8, 8, clearq)
+RVVCALL(OPFVF2, vfsgnj_vf_h, OP_UUU_H, H2, H2, fsgnj16)
+RVVCALL(OPFVF2, vfsgnj_vf_w, OP_UUU_W, H4, H4, fsgnj32)
+RVVCALL(OPFVF2, vfsgnj_vf_d, OP_UUU_D, H8, H8, fsgnj64)
+GEN_VEXT_VF(vfsgnj_vf_h, 2, 2, clearh)
+GEN_VEXT_VF(vfsgnj_vf_w, 4, 4, clearl)
+GEN_VEXT_VF(vfsgnj_vf_d, 8, 8, clearq)
+
+static uint16_t fsgnjn16(uint16_t a, uint16_t b, float_status *s)
+{
+ return deposit64(~b, 0, 15, a);
+}
+
+static uint32_t fsgnjn32(uint32_t a, uint32_t b, float_status *s)
+{
+ return deposit64(~b, 0, 31, a);
+}
+
+static uint64_t fsgnjn64(uint64_t a, uint64_t b, float_status *s)
+{
+ return deposit64(~b, 0, 63, a);
+}
+
+RVVCALL(OPFVV2, vfsgnjn_vv_h, OP_UUU_H, H2, H2, H2, fsgnjn16)
+RVVCALL(OPFVV2, vfsgnjn_vv_w, OP_UUU_W, H4, H4, H4, fsgnjn32)
+RVVCALL(OPFVV2, vfsgnjn_vv_d, OP_UUU_D, H8, H8, H8, fsgnjn64)
+GEN_VEXT_VV_ENV(vfsgnjn_vv_h, 2, 2, clearh)
+GEN_VEXT_VV_ENV(vfsgnjn_vv_w, 4, 4, clearl)
+GEN_VEXT_VV_ENV(vfsgnjn_vv_d, 8, 8, clearq)
+RVVCALL(OPFVF2, vfsgnjn_vf_h, OP_UUU_H, H2, H2, fsgnjn16)
+RVVCALL(OPFVF2, vfsgnjn_vf_w, OP_UUU_W, H4, H4, fsgnjn32)
+RVVCALL(OPFVF2, vfsgnjn_vf_d, OP_UUU_D, H8, H8, fsgnjn64)
+GEN_VEXT_VF(vfsgnjn_vf_h, 2, 2, clearh)
+GEN_VEXT_VF(vfsgnjn_vf_w, 4, 4, clearl)
+GEN_VEXT_VF(vfsgnjn_vf_d, 8, 8, clearq)
+
+static uint16_t fsgnjx16(uint16_t a, uint16_t b, float_status *s)
+{
+ return deposit64(b ^ a, 0, 15, a);
+}
+
+static uint32_t fsgnjx32(uint32_t a, uint32_t b, float_status *s)
+{
+ return deposit64(b ^ a, 0, 31, a);
+}
+
+static uint64_t fsgnjx64(uint64_t a, uint64_t b, float_status *s)
+{
+ return deposit64(b ^ a, 0, 63, a);
+}
+
+RVVCALL(OPFVV2, vfsgnjx_vv_h, OP_UUU_H, H2, H2, H2, fsgnjx16)
+RVVCALL(OPFVV2, vfsgnjx_vv_w, OP_UUU_W, H4, H4, H4, fsgnjx32)
+RVVCALL(OPFVV2, vfsgnjx_vv_d, OP_UUU_D, H8, H8, H8, fsgnjx64)
+GEN_VEXT_VV_ENV(vfsgnjx_vv_h, 2, 2, clearh)
+GEN_VEXT_VV_ENV(vfsgnjx_vv_w, 4, 4, clearl)
+GEN_VEXT_VV_ENV(vfsgnjx_vv_d, 8, 8, clearq)
+RVVCALL(OPFVF2, vfsgnjx_vf_h, OP_UUU_H, H2, H2, fsgnjx16)
+RVVCALL(OPFVF2, vfsgnjx_vf_w, OP_UUU_W, H4, H4, fsgnjx32)
+RVVCALL(OPFVF2, vfsgnjx_vf_d, OP_UUU_D, H8, H8, fsgnjx64)
+GEN_VEXT_VF(vfsgnjx_vf_h, 2, 2, clearh)
+GEN_VEXT_VF(vfsgnjx_vf_w, 4, 4, clearl)
+GEN_VEXT_VF(vfsgnjx_vf_d, 8, 8, clearq)
--
2.23.0
next prev parent reply other threads:[~2020-06-10 12:55 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-10 11:36 [PATCH v9 00/61] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 01/61] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 02/61] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 03/61] target/riscv: support vector extension csr LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 04/61] target/riscv: add vector configure instruction LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 05/61] target/riscv: add an internals.h header LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 06/61] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 07/61] target/riscv: add vector index " LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 08/61] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 09/61] target/riscv: add vector amo operations LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 10/61] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 11/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 13/61] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 14/61] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 15/61] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 16/61] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 17/61] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 18/61] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 19/61] target/riscv: vector integer divide instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 20/61] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 21/61] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 22/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 23/61] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 24/61] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 25/61] target/riscv: vector single-width averaging " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 27/61] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 28/61] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 29/61] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 30/61] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 31/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 32/61] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 33/61] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 35/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 36/61] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 37/61] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-06-10 11:37 ` LIU Zhiwei [this message]
2020-06-10 11:37 ` [PATCH v9 39/61] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-06-10 17:33 ` Richard Henderson
2020-06-11 1:11 ` LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 40/61] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 41/61] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 42/61] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 43/61] target/riscv: widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 44/61] target/riscv: narrowing " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 45/61] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 46/61] target/riscv: vector wideing " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 47/61] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 48/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 49/61] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 50/61] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 51/61] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 52/61] target/riscv: set-X-first " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 53/61] target/riscv: vector iota instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 54/61] target/riscv: vector element index instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 55/61] target/riscv: integer extract instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 56/61] target/riscv: integer scalar move instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 57/61] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-06-20 0:44 ` Alistair Francis
2020-06-20 1:09 ` LIU Zhiwei
2020-06-20 1:06 ` Alistair Francis
2020-06-20 1:40 ` LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 58/61] target/riscv: vector slide instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 59/61] target/riscv: vector register gather instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 60/61] target/riscv: vector compress instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 61/61] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
2020-06-10 15:37 ` [PATCH v9 00/61] target/riscv: support vector extension v0.7.1 no-reply
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