From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com,
wenmeng_zhang@c-sky.com,
Alistair Francis <alistair.francis@wdc.com>,
palmer@dabbelt.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v9 40/61] target/riscv: vector floating-point classify instructions
Date: Wed, 10 Jun 2020 19:37:27 +0800 [thread overview]
Message-ID: <20200610113748.4754-41-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200610113748.4754-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/fpu_helper.c | 33 +--------
target/riscv/helper.h | 4 ++
target/riscv/insn32.decode | 1 +
target/riscv/insn_trans/trans_rvv.inc.c | 3 +
target/riscv/internals.h | 5 ++
target/riscv/vector_helper.c | 91 +++++++++++++++++++++++++
6 files changed, 107 insertions(+), 30 deletions(-)
diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c
index 0b79562a69..4379756dc4 100644
--- a/target/riscv/fpu_helper.c
+++ b/target/riscv/fpu_helper.c
@@ -22,6 +22,7 @@
#include "exec/exec-all.h"
#include "exec/helper-proto.h"
#include "fpu/softfloat.h"
+#include "internals.h"
target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
{
@@ -230,21 +231,7 @@ uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
target_ulong helper_fclass_s(uint64_t frs1)
{
- float32 f = frs1;
- bool sign = float32_is_neg(f);
-
- if (float32_is_infinity(f)) {
- return sign ? 1 << 0 : 1 << 7;
- } else if (float32_is_zero(f)) {
- return sign ? 1 << 3 : 1 << 4;
- } else if (float32_is_zero_or_denormal(f)) {
- return sign ? 1 << 2 : 1 << 5;
- } else if (float32_is_any_nan(f)) {
- float_status s = { }; /* for snan_bit_is_one */
- return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
- } else {
- return sign ? 1 << 1 : 1 << 6;
- }
+ return fclass_s(frs1);
}
uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
@@ -353,19 +340,5 @@ uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
target_ulong helper_fclass_d(uint64_t frs1)
{
- float64 f = frs1;
- bool sign = float64_is_neg(f);
-
- if (float64_is_infinity(f)) {
- return sign ? 1 << 0 : 1 << 7;
- } else if (float64_is_zero(f)) {
- return sign ? 1 << 3 : 1 << 4;
- } else if (float64_is_zero_or_denormal(f)) {
- return sign ? 1 << 2 : 1 << 5;
- } else if (float64_is_any_nan(f)) {
- float_status s = { }; /* for snan_bit_is_one */
- return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
- } else {
- return sign ? 1 << 1 : 1 << 6;
- }
+ return fclass_d(frs1);
}
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index bedd4d0114..23b268df90 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -990,3 +990,7 @@ DEF_HELPER_6(vmford_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vmford_vf_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmford_vf_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vmford_vf_d, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_5(vfclass_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfclass_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index b0f1c54d53..23e80fe954 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -512,6 +512,7 @@ vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
vmford_vv 011010 . ..... ..... 001 ..... 1010111 @r_vm
vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
+vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 11473b8f72..80058669f0 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2181,3 +2181,6 @@ GEN_OPFVF_TRANS(vmfle_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfgt_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmfge_vf, opfvf_cmp_check)
GEN_OPFVF_TRANS(vmford_vf, opfvf_cmp_check)
+
+/* Vector Floating-Point Classify Instruction */
+GEN_OPFV_TRANS(vfclass_v, opfv_check)
diff --git a/target/riscv/internals.h b/target/riscv/internals.h
index e59e8b30ad..f3cea478f7 100644
--- a/target/riscv/internals.h
+++ b/target/riscv/internals.h
@@ -27,4 +27,9 @@ FIELD(VDATA, VM, 8, 1)
FIELD(VDATA, LMUL, 9, 2)
FIELD(VDATA, NF, 11, 4)
FIELD(VDATA, WD, 11, 1)
+
+/* float point classify helpers */
+target_ulong fclass_h(uint64_t frs1);
+target_ulong fclass_s(uint64_t frs1);
+target_ulong fclass_d(uint64_t frs1);
#endif
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f4264c51b5..b0ccb32de0 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4103,3 +4103,94 @@ GEN_VEXT_CMP_VV_ENV(vmford_vv_d, uint64_t, H8, !float64_unordered_quiet)
GEN_VEXT_CMP_VF(vmford_vf_h, uint16_t, H2, !float16_unordered_quiet)
GEN_VEXT_CMP_VF(vmford_vf_w, uint32_t, H4, !float32_unordered_quiet)
GEN_VEXT_CMP_VF(vmford_vf_d, uint64_t, H8, !float64_unordered_quiet)
+
+/* Vector Floating-Point Classify Instruction */
+#define OPIVV1(NAME, TD, T2, TX2, HD, HS2, OP) \
+static void do_##NAME(void *vd, void *vs2, int i) \
+{ \
+ TX2 s2 = *((T2 *)vs2 + HS2(i)); \
+ *((TD *)vd + HD(i)) = OP(s2); \
+}
+
+#define GEN_VEXT_V(NAME, ESZ, DSZ, CLEAR_FN) \
+void HELPER(NAME)(void *vd, void *v0, void *vs2, \
+ CPURISCVState *env, uint32_t desc) \
+{ \
+ uint32_t vlmax = vext_maxsz(desc) / ESZ; \
+ uint32_t mlen = vext_mlen(desc); \
+ uint32_t vm = vext_vm(desc); \
+ uint32_t vl = env->vl; \
+ uint32_t i; \
+ \
+ for (i = 0; i < vl; i++) { \
+ if (!vm && !vext_elem_mask(v0, mlen, i)) { \
+ continue; \
+ } \
+ do_##NAME(vd, vs2, i); \
+ } \
+ CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \
+}
+
+target_ulong fclass_h(uint64_t frs1)
+{
+ float16 f = frs1;
+ bool sign = float16_is_neg(f);
+
+ if (float16_is_infinity(f)) {
+ return sign ? 1 << 0 : 1 << 7;
+ } else if (float16_is_zero(f)) {
+ return sign ? 1 << 3 : 1 << 4;
+ } else if (float16_is_zero_or_denormal(f)) {
+ return sign ? 1 << 2 : 1 << 5;
+ } else if (float16_is_any_nan(f)) {
+ float_status s = { }; /* for snan_bit_is_one */
+ return float16_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
+ } else {
+ return sign ? 1 << 1 : 1 << 6;
+ }
+}
+
+target_ulong fclass_s(uint64_t frs1)
+{
+ float32 f = frs1;
+ bool sign = float32_is_neg(f);
+
+ if (float32_is_infinity(f)) {
+ return sign ? 1 << 0 : 1 << 7;
+ } else if (float32_is_zero(f)) {
+ return sign ? 1 << 3 : 1 << 4;
+ } else if (float32_is_zero_or_denormal(f)) {
+ return sign ? 1 << 2 : 1 << 5;
+ } else if (float32_is_any_nan(f)) {
+ float_status s = { }; /* for snan_bit_is_one */
+ return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
+ } else {
+ return sign ? 1 << 1 : 1 << 6;
+ }
+}
+
+target_ulong fclass_d(uint64_t frs1)
+{
+ float64 f = frs1;
+ bool sign = float64_is_neg(f);
+
+ if (float64_is_infinity(f)) {
+ return sign ? 1 << 0 : 1 << 7;
+ } else if (float64_is_zero(f)) {
+ return sign ? 1 << 3 : 1 << 4;
+ } else if (float64_is_zero_or_denormal(f)) {
+ return sign ? 1 << 2 : 1 << 5;
+ } else if (float64_is_any_nan(f)) {
+ float_status s = { }; /* for snan_bit_is_one */
+ return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8;
+ } else {
+ return sign ? 1 << 1 : 1 << 6;
+ }
+}
+
+RVVCALL(OPIVV1, vfclass_v_h, OP_UU_H, H2, H2, fclass_h)
+RVVCALL(OPIVV1, vfclass_v_w, OP_UU_W, H4, H4, fclass_s)
+RVVCALL(OPIVV1, vfclass_v_d, OP_UU_D, H8, H8, fclass_d)
+GEN_VEXT_V(vfclass_v_h, 2, 2, clearh)
+GEN_VEXT_V(vfclass_v_w, 4, 4, clearl)
+GEN_VEXT_V(vfclass_v_d, 8, 8, clearq)
--
2.23.0
next prev parent reply other threads:[~2020-06-10 12:59 UTC|newest]
Thread overview: 69+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-10 11:36 [PATCH v9 00/61] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 01/61] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 02/61] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 03/61] target/riscv: support vector extension csr LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 04/61] target/riscv: add vector configure instruction LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 05/61] target/riscv: add an internals.h header LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 06/61] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 07/61] target/riscv: add vector index " LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 08/61] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 09/61] target/riscv: add vector amo operations LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 10/61] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 11/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:36 ` [PATCH v9 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 13/61] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 14/61] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 15/61] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 16/61] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 17/61] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 18/61] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 19/61] target/riscv: vector integer divide instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 20/61] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 21/61] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 22/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 23/61] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 24/61] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 25/61] target/riscv: vector single-width averaging " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 27/61] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 28/61] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 29/61] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 30/61] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 31/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 32/61] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 33/61] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 35/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 36/61] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 37/61] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 38/61] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 39/61] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-06-10 17:33 ` Richard Henderson
2020-06-11 1:11 ` LIU Zhiwei
2020-06-10 11:37 ` LIU Zhiwei [this message]
2020-06-10 11:37 ` [PATCH v9 41/61] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 42/61] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 43/61] target/riscv: widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 44/61] target/riscv: narrowing " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 45/61] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 46/61] target/riscv: vector wideing " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 47/61] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 48/61] target/riscv: vector widening " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 49/61] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 50/61] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 51/61] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 52/61] target/riscv: set-X-first " LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 53/61] target/riscv: vector iota instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 54/61] target/riscv: vector element index instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 55/61] target/riscv: integer extract instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 56/61] target/riscv: integer scalar move instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 57/61] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-06-20 0:44 ` Alistair Francis
2020-06-20 1:09 ` LIU Zhiwei
2020-06-20 1:06 ` Alistair Francis
2020-06-20 1:40 ` LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 58/61] target/riscv: vector slide instructions LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 59/61] target/riscv: vector register gather instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 60/61] target/riscv: vector compress instruction LIU Zhiwei
2020-06-10 11:37 ` [PATCH v9 61/61] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
2020-06-10 15:37 ` [PATCH v9 00/61] target/riscv: support vector extension v0.7.1 no-reply
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