From: Lijun Pan <ljp@linux.ibm.com>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: Lijun Pan <ljp@linux.ibm.com>
Subject: [PATCH 2/6] target/ppc: add vmulld instruction
Date: Fri, 12 Jun 2020 23:20:25 -0500 [thread overview]
Message-ID: <20200613042029.22321-3-ljp@linux.ibm.com> (raw)
In-Reply-To: <20200613042029.22321-1-ljp@linux.ibm.com>
vmulld: Vector Multiply Low Doubleword.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
target/ppc/helper.h | 1 +
target/ppc/int_helper.c | 1 +
target/ppc/translate/vmx-impl.inc.c | 1 +
target/ppc/translate/vmx-ops.inc.c | 1 +
4 files changed, 4 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 2dfa1c6942..c3f087ccb3 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -185,6 +185,7 @@ DEF_HELPER_3(vmuloub, void, avr, avr, avr)
DEF_HELPER_3(vmulouh, void, avr, avr, avr)
DEF_HELPER_3(vmulouw, void, avr, avr, avr)
DEF_HELPER_3(vmuluwm, void, avr, avr, avr)
+DEF_HELPER_3(vmulld, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_3(vsrv, void, avr, avr, avr)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index be53cd6f68..afbcdd05b4 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -533,6 +533,7 @@ void helper_vprtybq(ppc_avr_t *r, ppc_avr_t *b)
} \
}
VARITH_DO(muluwm, *, u32)
+VARITH_DO(mulld, *, s64)
#undef VARITH_DO
#undef VARITH
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 403ed3a01c..4ee1df48f2 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -807,6 +807,7 @@ GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
GEN_VXFORM(vmulosb, 4, 4);
GEN_VXFORM(vmulosh, 4, 5);
GEN_VXFORM(vmulosw, 4, 6);
+GEN_VXFORM(vmulld, 4, 7);
GEN_VXFORM(vmuleub, 4, 8);
GEN_VXFORM(vmuleuh, 4, 9);
GEN_VXFORM(vmuleuw, 4, 10);
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index 84e05fb827..499bed0a44 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -104,6 +104,7 @@ GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vmulosb, 4, 4),
GEN_VXFORM(vmulosh, 4, 5),
GEN_VXFORM_207(vmulosw, 4, 6),
+GEN_VXFORM_300(vmulld, 4, 7),
GEN_VXFORM(vmuleub, 4, 8),
GEN_VXFORM(vmuleuh, 4, 9),
GEN_VXFORM_207(vmuleuw, 4, 10),
--
2.23.0
next prev parent reply other threads:[~2020-06-13 4:21 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-13 4:20 [PATCH 0/6] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
2020-06-13 4:20 ` [PATCH 1/6] target/ppc: add byte-reverse br[dwh] instructions Lijun Pan
2020-06-18 23:19 ` Richard Henderson
2020-06-19 5:24 ` Lijun Pan
2020-06-19 21:08 ` Richard Henderson
2020-06-13 4:20 ` Lijun Pan [this message]
2020-06-18 23:27 ` [PATCH 2/6] target/ppc: add vmulld instruction Richard Henderson
2020-06-19 5:30 ` Lijun Pan
2020-06-19 21:16 ` Richard Henderson
2020-06-13 4:20 ` [PATCH 3/6] targetc/ppc: add vmulh{su}w instructions Lijun Pan
2020-06-18 23:29 ` Richard Henderson
2020-06-19 5:37 ` Lijun Pan
2020-06-19 21:17 ` Richard Henderson
2020-06-13 4:20 ` [PATCH 4/6] target/ppc: add vmulh{su}d instructions Lijun Pan
2020-06-18 23:32 ` Richard Henderson
2020-06-13 4:20 ` [PATCH 5/6] fix the prototype of muls64/mulu64 Lijun Pan
2020-06-18 23:46 ` Richard Henderson
2020-06-13 4:20 ` [PATCH 6/6] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions Lijun Pan
2020-06-18 23:46 ` Richard Henderson
2020-06-13 4:47 ` [PATCH 0/6] Add several Power ISA 3.1 32/64-bit vector instructions no-reply
2020-06-15 8:49 ` David Gibson
2020-06-15 17:36 ` Cédric Le Goater
2020-06-15 20:54 ` Lijun Pan
2020-06-16 6:00 ` Cédric Le Goater
2020-06-18 23:51 ` Richard Henderson
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