From: Lijun Pan <ljp@linux.ibm.com>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: Lijun Pan <ljp@linux.ibm.com>
Subject: [PATCH 4/6] target/ppc: add vmulh{su}d instructions
Date: Fri, 12 Jun 2020 23:20:27 -0500 [thread overview]
Message-ID: <20200613042029.22321-5-ljp@linux.ibm.com> (raw)
In-Reply-To: <20200613042029.22321-1-ljp@linux.ibm.com>
vmulhsd: Vector Multiply High Signed Doubleword
vmulhud: Vector Multiply High Unsigned Doubleword
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
target/ppc/helper.h | 2 ++
target/ppc/int_helper.c | 24 ++++++++++++++++++++++++
target/ppc/translate/vmx-impl.inc.c | 2 ++
target/ppc/translate/vmx-ops.inc.c | 2 ++
4 files changed, 30 insertions(+)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 6d4a3536eb..1aed2087cf 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -188,6 +188,8 @@ DEF_HELPER_3(vmuluwm, void, avr, avr, avr)
DEF_HELPER_3(vmulld, void, avr, avr, avr)
DEF_HELPER_3(vmulhsw, void, avr, avr, avr)
DEF_HELPER_3(vmulhuw, void, avr, avr, avr)
+DEF_HELPER_3(vmulhsd, void, avr, avr, avr)
+DEF_HELPER_3(vmulhud, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_3(vsrv, void, avr, avr, avr)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index 4bb3b7e928..6c401d41f6 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -523,6 +523,30 @@ void helper_vprtybq(ppc_avr_t *r, ppc_avr_t *b)
r->VsrD(0) = 0;
}
+void helper_vmulhsd(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+ uint64_t h64 = 0;
+ uint64_t l64 = 0;
+
+ for (i = 0; i < 2; i++) {
+ muls64(&l64, &h64, a->s64[i], b->s64[i]);
+ r->s64[i] = h64;
+ }
+}
+
+void helper_vmulhud(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+ uint64_t h64 = 0;
+ uint64_t l64 = 0;
+
+ for (i = 0; i < 2; i++) {
+ mulu64(&l64, &h64, a->s64[i], b->s64[i]);
+ r->u64[i] = h64;
+ }
+}
+
#define VMULH_DO(name, op, element, cast_orig, cast_temp) \
void helper_vmulh##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
{ \
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 2c35559c52..a9e7e7c3fe 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -812,6 +812,7 @@ GEN_VXFORM(vmuleub, 4, 8);
GEN_VXFORM(vmuleuh, 4, 9);
GEN_VXFORM(vmuleuw, 4, 10);
GEN_VXFORM(vmulhuw, 4, 10);
+GEN_VXFORM(vmulhud, 4, 11);
GEN_VXFORM_DUAL(vmuleuw, PPC_ALTIVEC, PPC_NONE,
vmulhuw, PPC_NONE, PPC2_ISA300);
GEN_VXFORM(vmulesb, 4, 12);
@@ -820,6 +821,7 @@ GEN_VXFORM(vmulesw, 4, 14);
GEN_VXFORM(vmulhsw, 4, 14);
GEN_VXFORM_DUAL(vmulesw, PPC_ALTIVEC, PPC_NONE,
vmulhsw, PPC_NONE, PPC2_ISA300);
+GEN_VXFORM(vmulhsd, 4, 15);
GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index 1d8238a718..719fecbaa3 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -108,9 +108,11 @@ GEN_VXFORM_300(vmulld, 4, 7),
GEN_VXFORM(vmuleub, 4, 8),
GEN_VXFORM(vmuleuh, 4, 9),
GEN_VXFORM_DUAL(vmuleuw, vmulhuw, 4, 10, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_300(vmulhud, 4, 11),
GEN_VXFORM(vmulesb, 4, 12),
GEN_VXFORM(vmulesh, 4, 13),
GEN_VXFORM_DUAL(vmulesw, vmulhsw, 4, 14, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_300(vmulhsd, 4, 15),
GEN_VXFORM(vslb, 2, 4),
GEN_VXFORM(vslh, 2, 5),
GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE),
--
2.23.0
next prev parent reply other threads:[~2020-06-13 4:23 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-13 4:20 [PATCH 0/6] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
2020-06-13 4:20 ` [PATCH 1/6] target/ppc: add byte-reverse br[dwh] instructions Lijun Pan
2020-06-18 23:19 ` Richard Henderson
2020-06-19 5:24 ` Lijun Pan
2020-06-19 21:08 ` Richard Henderson
2020-06-13 4:20 ` [PATCH 2/6] target/ppc: add vmulld instruction Lijun Pan
2020-06-18 23:27 ` Richard Henderson
2020-06-19 5:30 ` Lijun Pan
2020-06-19 21:16 ` Richard Henderson
2020-06-13 4:20 ` [PATCH 3/6] targetc/ppc: add vmulh{su}w instructions Lijun Pan
2020-06-18 23:29 ` Richard Henderson
2020-06-19 5:37 ` Lijun Pan
2020-06-19 21:17 ` Richard Henderson
2020-06-13 4:20 ` Lijun Pan [this message]
2020-06-18 23:32 ` [PATCH 4/6] target/ppc: add vmulh{su}d instructions Richard Henderson
2020-06-13 4:20 ` [PATCH 5/6] fix the prototype of muls64/mulu64 Lijun Pan
2020-06-18 23:46 ` Richard Henderson
2020-06-13 4:20 ` [PATCH 6/6] target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions Lijun Pan
2020-06-18 23:46 ` Richard Henderson
2020-06-13 4:47 ` [PATCH 0/6] Add several Power ISA 3.1 32/64-bit vector instructions no-reply
2020-06-15 8:49 ` David Gibson
2020-06-15 17:36 ` Cédric Le Goater
2020-06-15 20:54 ` Lijun Pan
2020-06-16 6:00 ` Cédric Le Goater
2020-06-18 23:51 ` Richard Henderson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200613042029.22321-5-ljp@linux.ibm.com \
--to=ljp@linux.ibm.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).