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Wed, 17 Jun 2020 10:28:37 +0000 (UTC) Date: Wed, 17 Jun 2020 11:28:34 +0100 From: "Dr. David Alan Gilbert" To: Daniel =?iso-8859-1?Q?P=2E_Berrang=E9?= Subject: Re: ovmf / PCI passthrough impaired due to very limiting PCI64 aperture Message-ID: <20200617102834.GB2776@work-vm> References: <99779e9c-f05f-501b-b4be-ff719f140a88@canonical.com> <20200616165043.24y2cp53axk7uggy@sirius.home.kraxel.org> <20200616165746.GH2788@work-vm> <20200616171021.GV2366737@habkost.net> <20200617085033.GB568347@redhat.com> MIME-Version: 1.0 In-Reply-To: <20200617085033.GB568347@redhat.com> User-Agent: Mutt/1.14.0 (2020-05-02) X-Scanned-By: MIMEDefang 2.79 on 10.5.11.12 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=dgilbert@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Content-Disposition: inline Received-SPF: pass client-ip=207.211.31.81; envelope-from=dgilbert@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/17 01:42:42 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pedro.principeza@canonical.com, Eduardo Habkost , dann.frazier@canonical.com, "Guilherme G. Piccoli" , qemu-devel@nongnu.org, christian.ehrhardt@canonical.com, Gerd Hoffmann , lersek@redhat.com, fw@gpiccoli.net Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" * Daniel P. Berrangé (berrange@redhat.com) wrote: > On Tue, Jun 16, 2020 at 01:10:21PM -0400, Eduardo Habkost wrote: > > On Tue, Jun 16, 2020 at 05:57:46PM +0100, Dr. David Alan Gilbert wrote: > > > * Gerd Hoffmann (kraxel@redhat.com) wrote: > > > > Hi, > > > > > > > > > (a) We could rely in the guest physbits to calculate the PCI64 aperture. > > > > > > > > I'd love to do that. Move the 64-bit I/O window as high as possible and > > > > use -- say -- 25% of the physical address space for it. > > > > > > > > Problem is we can't. > > > > > > > > > failure. Also, if the users are not setting the physbits in the guest, > > > > > there must be a default (seems to be 40bit according to my experiments), > > > > > seems to be a good idea to rely on that. > > > > > > > > Yes, 40 is the default, and it is used *even if the host supports less > > > > than that*. Typical values I've seen for intel hardware are 36 and 39. > > > > 39 is used even by recent hardware (not the xeons, but check out a > > > > laptop or a nuc). > > > > > > > > > If guest physbits is 40, why to have OVMF limiting it to 36, right? > > > > > > > > Things will explode in case OVMF uses more physbits than the host > > > > supports (host physbits limit applies to ept too). In other words: OVMF > > > > can't trust the guest physbits, so it is conservative to be on the safe > > > > side. > > > > > > > > If we can somehow make a *trustable* physbits value available to the > > > > guest, then yes, we can go that route. But the guest physbits we have > > > > today unfortunately don't cut it. > > > > > > In downstream RH qemu, we run with host-physbits as default; so it's reasonably > > > trustworthy; of course that doesn't help you across a migration between > > > hosts with different sizes (e.g. an E5 Xeon to an E3). > > > Changing upstream to do the same would seem sensible to me, but it's not > > > a foolproof config. > > > > Yeah, to make it really trustworthy we would need to prevent > > migration to hosts with mismatching phys sizes. We would need to > > communicate that to the guest somehow (with new hypervisor CPUID > > flags, maybe). > > QEMU should be able to validate the hostphysbits >= guestphysbits when > accepting incoming migration, and abort it. Yeh, there's an outstanding request to validate other CPU flags as well. > Meanwhile libvirt should be enhanced to report hostphysbits, so that > management apps can determine that they shouldn't even pick bad hosts > in the first place. Sounds reasonable. Note there are a couple of other considerations when choosing the physbits as reported to the guest: a) TCG's view - I think it had a fixed size of 40 bits, but I haven't dug into it. b) We recently gained 'host-phys-bits-limit' which when used with host-phys-bits lets you take the host value but then limit it. Eduardo seems to have done that to limit the guest from flipping into 5-level page tables. Hmm I've not tried with chips that do 5-level - but maybe we also need this if you expect to migrate to hosts that don't have it. (I've also got a vague memory that there's a limit in some IOMMUs address sizes, but I can't remember what the details were). Dave > > Regards, > Daniel > -- > |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| > |: https://libvirt.org -o- https://fstop138.berrange.com :| > |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :| -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK