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Fri, 19 Jun 2020 09:45:29 +0000 (UTC) Date: Fri, 19 Jun 2020 11:45:26 +0200 From: Cornelia Huck To: David Hildenbrand Subject: Re: [PATCH v3 0/9] Generalize memory encryption models Message-ID: <20200619114526.6a6f70c6.cohuck@redhat.com> In-Reply-To: References: <20200619020602.118306-1-david@gibson.dropbear.id.au> Organization: Red Hat GmbH MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 Received-SPF: pass client-ip=205.139.110.120; envelope-from=cohuck@redhat.com; helo=us-smtp-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/19 05:19:18 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: pair@us.ibm.com, brijesh.singh@amd.com, frankja@linux.ibm.com, kvm@vger.kernel.org, mst@redhat.com, qemu-devel@nongnu.org, Eduardo Habkost , dgilbert@redhat.com, pasic@linux.ibm.com, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, pbonzini@redhat.com, Richard Henderson , mdroth@linux.vnet.ibm.com, David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Fri, 19 Jun 2020 10:28:22 +0200 David Hildenbrand wrote: > On 19.06.20 04:05, David Gibson wrote: > > A number of hardware platforms are implementing mechanisms whereby the > > hypervisor does not have unfettered access to guest memory, in order > > to mitigate the security impact of a compromised hypervisor. > > > > AMD's SEV implements this with in-cpu memory encryption, and Intel has > > its own memory encryption mechanism. POWER has an upcoming mechanism > > to accomplish this in a different way, using a new memory protection > > level plus a small trusted ultravisor. s390 also has a protected > > execution environment. > > Each architecture finds its own way to vandalize the original > architecture, some in more extreme/obscure ways than others. I guess in > the long term we'll regret most of that, but what do I know :) > > > > > The current code (committed or draft) for these features has each > > platform's version configured entirely differently. That doesn't seem > > ideal for users, or particularly for management layers. > > > > AMD SEV introduces a notionally generic machine option > > "machine-encryption", but it doesn't actually cover any cases other > > than SEV. > > > > This series is a proposal to at least partially unify configuration > > for these mechanisms, by renaming and generalizing AMD's > > "memory-encryption" property. It is replaced by a > > "host-trust-limitation" property pointing to a platform specific > > object which configures and manages the specific details. > > > > I consider the property name sub-optimal. Yes, I am aware that there are > other approaches being discussed on the KVM list to disallow access to > guest memory without memory encryption. (most of them sound like people > are trying to convert KVM into XEN, but again, what do I know ... :) ) > > "host-trust-limitation" sounds like "I am the hypervisor, I configure > limited trust into myself". Also, "untrusted-host" would be a little bit > nicer (I think trust is a black/white thing). > > However, once we have multiple options to protect a guest (memory > encryption, unmapping guest pages ,...) the name will no longer really > suffice to configure QEMU, no? Hm... we could have a property that accepts bits indicating where the actual limitation lies. Different parts of the code could then make more fine-grained decisions of what needs to be done. Feels a bit overengineered today; but maybe there's already stuff with different semantics in the pipeline somewhere? > > > For now this series covers just AMD SEV and POWER PEF. I'm hoping it > > can be extended to cover the Intel and s390 mechanisms as well, > > though. > > The only approach on s390x to not glue command line properties to the > cpu model would be to remove the CPU model feature and replace it by the > command line parameter. But that would, of course, be an incompatible break. Yuck. We still need to provide the cpu feature to the *guest* in any case, no? > > How do upper layers actually figure out if memory encryption etc is > available? on s390x, it's simply via the expanded host CPU model. >