From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com,
wenmeng_zhang@c-sky.com,
Alistair Francis <alistair.francis@wdc.com>,
palmer@dabbelt.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v10 15/61] target/riscv: vector narrowing integer right shift instructions
Date: Sat, 20 Jun 2020 12:36:15 +0800 [thread overview]
Message-ID: <20200620043701.1323-16-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200620043701.1323-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 13 ++++
target/riscv/insn32.decode | 6 ++
target/riscv/insn_trans/trans_rvv.inc.c | 90 +++++++++++++++++++++++++
target/riscv/vector_helper.c | 14 ++++
4 files changed, 123 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 6805bf7dbd..1ec2202814 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -432,3 +432,16 @@ DEF_HELPER_6(vsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vsra_vx_d, void, ptr, ptr, tl, ptr, env, i32)
+
+DEF_HELPER_6(vnsrl_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsra_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vnsrl_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsrl_vx_w, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_vx_b, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_vx_h, void, ptr, ptr, tl, ptr, env, i32)
+DEF_HELPER_6(vnsra_vx_w, void, ptr, ptr, tl, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index e5334230df..435415f9f9 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -331,6 +331,12 @@ vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
+vnsrl_vv 101100 . ..... ..... 000 ..... 1010111 @r_vm
+vnsrl_vx 101100 . ..... ..... 100 ..... 1010111 @r_vm
+vnsrl_vi 101100 . ..... ..... 011 ..... 1010111 @r_vm
+vnsra_vv 101101 . ..... ..... 000 ..... 1010111 @r_vm
+vnsra_vx 101101 . ..... ..... 100 ..... 1010111 @r_vm
+vnsra_vi 101101 . ..... ..... 011 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 8ea7c437ee..87f9ee7f6c 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -1425,3 +1425,93 @@ GEN_OPIVX_GVEC_SHIFT_TRANS(vsra_vx, sars)
GEN_OPIVI_GVEC_TRANS(vsll_vi, 1, vsll_vx, shli)
GEN_OPIVI_GVEC_TRANS(vsrl_vi, 1, vsrl_vx, shri)
GEN_OPIVI_GVEC_TRANS(vsra_vi, 1, vsra_vx, sari)
+
+/* Vector Narrowing Integer Right Shift Instructions */
+static bool opivv_narrow_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, true) &&
+ vext_check_reg(s, a->rs1, false) &&
+ vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
+ 2 << s->lmul) &&
+ (s->lmul < 0x3) && (s->sew < 0x3));
+}
+
+/* OPIVV with NARROW */
+#define GEN_OPIVV_NARROW_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (opivv_narrow_check(s, a)) { \
+ uint32_t data = 0; \
+ static gen_helper_gvec_4_ptr * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ }; \
+ TCGLabel *over = gen_new_label(); \
+ tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_vl, 0, over); \
+ \
+ data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \
+ data = FIELD_DP32(data, VDATA, VM, a->vm); \
+ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
+ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
+ vreg_ofs(s, a->rs1), \
+ vreg_ofs(s, a->rs2), cpu_env, 0, \
+ s->vlen / 8, data, fns[s->sew]); \
+ gen_set_label(over); \
+ return true; \
+ } \
+ return false; \
+}
+GEN_OPIVV_NARROW_TRANS(vnsra_vv)
+GEN_OPIVV_NARROW_TRANS(vnsrl_vv)
+
+static bool opivx_narrow_check(DisasContext *s, arg_rmrr *a)
+{
+ return (vext_check_isa_ill(s) &&
+ vext_check_overlap_mask(s, a->rd, a->vm, false) &&
+ vext_check_reg(s, a->rd, false) &&
+ vext_check_reg(s, a->rs2, true) &&
+ vext_check_overlap_group(a->rd, 1 << s->lmul, a->rs2,
+ 2 << s->lmul) &&
+ (s->lmul < 0x3) && (s->sew < 0x3));
+}
+
+/* OPIVX with NARROW */
+#define GEN_OPIVX_NARROW_TRANS(NAME) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (opivx_narrow_check(s, a)) { \
+ static gen_helper_opivx * const fns[3] = { \
+ gen_helper_##NAME##_b, \
+ gen_helper_##NAME##_h, \
+ gen_helper_##NAME##_w, \
+ }; \
+ return opivx_trans(a->rd, a->rs1, a->rs2, a->vm, fns[s->sew], s);\
+ } \
+ return false; \
+}
+
+GEN_OPIVX_NARROW_TRANS(vnsra_vx)
+GEN_OPIVX_NARROW_TRANS(vnsrl_vx)
+
+/* OPIVI with NARROW */
+#define GEN_OPIVI_NARROW_TRANS(NAME, ZX, OPIVX) \
+static bool trans_##NAME(DisasContext *s, arg_rmrr *a) \
+{ \
+ if (opivx_narrow_check(s, a)) { \
+ static gen_helper_opivx * const fns[3] = { \
+ gen_helper_##OPIVX##_b, \
+ gen_helper_##OPIVX##_h, \
+ gen_helper_##OPIVX##_w, \
+ }; \
+ return opivi_trans(a->rd, a->rs1, a->rs2, a->vm, \
+ fns[s->sew], s, ZX); \
+ } \
+ return false; \
+}
+
+GEN_OPIVI_NARROW_TRANS(vnsra_vi, 1, vnsra_vx)
+GEN_OPIVI_NARROW_TRANS(vnsrl_vi, 1, vnsrl_vx)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index f63f06bd37..7b59719baa 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -1395,3 +1395,17 @@ GEN_VEXT_SHIFT_VX(vsra_vx_b, int8_t, int8_t, H1, H1, DO_SRL, 0x7, clearb)
GEN_VEXT_SHIFT_VX(vsra_vx_h, int16_t, int16_t, H2, H2, DO_SRL, 0xf, clearh)
GEN_VEXT_SHIFT_VX(vsra_vx_w, int32_t, int32_t, H4, H4, DO_SRL, 0x1f, clearl)
GEN_VEXT_SHIFT_VX(vsra_vx_d, int64_t, int64_t, H8, H8, DO_SRL, 0x3f, clearq)
+
+/* Vector Narrowing Integer Right Shift Instructions */
+GEN_VEXT_SHIFT_VV(vnsrl_vv_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
+GEN_VEXT_SHIFT_VV(vnsrl_vv_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
+GEN_VEXT_SHIFT_VV(vnsrl_vv_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
+GEN_VEXT_SHIFT_VV(vnsra_vv_b, uint8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
+GEN_VEXT_SHIFT_VV(vnsra_vv_h, uint16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
+GEN_VEXT_SHIFT_VV(vnsra_vv_w, uint32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
+GEN_VEXT_SHIFT_VX(vnsrl_vx_b, uint8_t, uint16_t, H1, H2, DO_SRL, 0xf, clearb)
+GEN_VEXT_SHIFT_VX(vnsrl_vx_h, uint16_t, uint32_t, H2, H4, DO_SRL, 0x1f, clearh)
+GEN_VEXT_SHIFT_VX(vnsrl_vx_w, uint32_t, uint64_t, H4, H8, DO_SRL, 0x3f, clearl)
+GEN_VEXT_SHIFT_VX(vnsra_vx_b, int8_t, int16_t, H1, H2, DO_SRL, 0xf, clearb)
+GEN_VEXT_SHIFT_VX(vnsra_vx_h, int16_t, int32_t, H2, H4, DO_SRL, 0x1f, clearh)
+GEN_VEXT_SHIFT_VX(vnsra_vx_w, int32_t, int64_t, H4, H8, DO_SRL, 0x3f, clearl)
--
2.23.0
next prev parent reply other threads:[~2020-06-20 5:08 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-20 4:36 [PATCH v10 00/61] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 01/61] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 02/61] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 03/61] target/riscv: support vector extension csr LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 04/61] target/riscv: add vector configure instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 05/61] target/riscv: add an internals.h header LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 06/61] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-06-23 16:52 ` Alistair Francis
2020-06-23 21:32 ` LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 07/61] target/riscv: add vector index " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 08/61] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 09/61] target/riscv: add vector amo operations LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 10/61] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 11/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 13/61] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 14/61] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-06-20 4:36 ` LIU Zhiwei [this message]
2020-06-20 4:36 ` [PATCH v10 16/61] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 17/61] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 18/61] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 19/61] target/riscv: vector integer divide instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 20/61] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 21/61] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 22/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 23/61] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 24/61] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 25/61] target/riscv: vector single-width averaging " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 27/61] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 28/61] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 29/61] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 30/61] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 31/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 32/61] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 33/61] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 35/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 36/61] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 37/61] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 38/61] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 39/61] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 40/61] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 41/61] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 42/61] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 43/61] target/riscv: widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 44/61] target/riscv: narrowing " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 45/61] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 46/61] target/riscv: vector wideing " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 47/61] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 48/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 49/61] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 50/61] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 51/61] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 52/61] target/riscv: set-X-first " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 53/61] target/riscv: vector iota instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 54/61] target/riscv: vector element index instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 55/61] target/riscv: integer extract instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 56/61] target/riscv: integer scalar move instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 57/61] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 58/61] target/riscv: vector slide instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 59/61] target/riscv: vector register gather instruction LIU Zhiwei
2020-06-20 4:37 ` [PATCH v10 60/61] target/riscv: vector compress instruction LIU Zhiwei
2020-06-20 4:37 ` [PATCH v10 61/61] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
-- strict thread matches above, loose matches on Subject: below --
2020-06-20 2:54 [PATCH v10 00/61] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-06-20 2:54 ` [PATCH v10 15/61] target/riscv: vector narrowing integer right shift instructions LIU Zhiwei
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200620043701.1323-16-zhiwei_liu@c-sky.com \
--to=zhiwei_liu@c-sky.com \
--cc=alistair.francis@wdc.com \
--cc=palmer@dabbelt.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=richard.henderson@linaro.org \
--cc=wenmeng_zhang@c-sky.com \
--cc=wxy194768@alibaba-inc.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).