From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com,
wenmeng_zhang@c-sky.com,
Alistair Francis <alistair.francis@wdc.com>,
palmer@dabbelt.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v10 42/61] target/riscv: vector floating-point/integer type-convert instructions
Date: Sat, 20 Jun 2020 12:36:42 +0800 [thread overview]
Message-ID: <20200620043701.1323-43-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200620043701.1323-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 13 ++++++++++
target/riscv/insn32.decode | 4 +++
target/riscv/insn_trans/trans_rvv.inc.c | 6 +++++
target/riscv/vector_helper.c | 33 +++++++++++++++++++++++++
4 files changed, 56 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 2c3f0a4e0c..d01e739607 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1004,3 +1004,16 @@ DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfmerge_vfm_h, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfmerge_vfm_w, void, ptr, ptr, i64, ptr, env, i32)
DEF_HELPER_6(vfmerge_vfm_d, void, ptr, ptr, i64, ptr, env, i32)
+
+DEF_HELPER_5(vfcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_xu_f_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_x_f_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_f_xu_v_d, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32)
+DEF_HELPER_5(vfcvt_f_x_v_d, void, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 38e7445a16..913c3b099b 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -517,6 +517,10 @@ vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm
vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
+vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm
+vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm
+vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm
+vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 51ee83255e..a2a851de87 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2222,3 +2222,9 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a)
}
return false;
}
+
+/* Single-Width Floating-Point/Integer Type-Convert Instructions */
+GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check)
+GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check)
+GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check)
+GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 5a0dd9304d..354d69b800 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4218,3 +4218,36 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \
GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh)
GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4, clearl)
GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8, clearq)
+
+/* Single-Width Floating-Point/Integer Type-Convert Instructions */
+/* vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */
+RVVCALL(OPFVV1, vfcvt_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16)
+RVVCALL(OPFVV1, vfcvt_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32)
+RVVCALL(OPFVV1, vfcvt_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64)
+GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4, 4, clearl)
+GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8, 8, clearq)
+
+/* vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. */
+RVVCALL(OPFVV1, vfcvt_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16)
+RVVCALL(OPFVV1, vfcvt_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32)
+RVVCALL(OPFVV1, vfcvt_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64)
+GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4, 4, clearl)
+GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8, 8, clearq)
+
+/* vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. */
+RVVCALL(OPFVV1, vfcvt_f_xu_v_h, OP_UU_H, H2, H2, uint16_to_float16)
+RVVCALL(OPFVV1, vfcvt_f_xu_v_w, OP_UU_W, H4, H4, uint32_to_float32)
+RVVCALL(OPFVV1, vfcvt_f_xu_v_d, OP_UU_D, H8, H8, uint64_to_float64)
+GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4, 4, clearl)
+GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8, 8, clearq)
+
+/* vfcvt.f.x.v vd, vs2, vm # Convert integer to float. */
+RVVCALL(OPFVV1, vfcvt_f_x_v_h, OP_UU_H, H2, H2, int16_to_float16)
+RVVCALL(OPFVV1, vfcvt_f_x_v_w, OP_UU_W, H4, H4, int32_to_float32)
+RVVCALL(OPFVV1, vfcvt_f_x_v_d, OP_UU_D, H8, H8, int64_to_float64)
+GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2, clearh)
+GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4, clearl)
+GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8, clearq)
--
2.23.0
next prev parent reply other threads:[~2020-06-20 6:03 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-20 4:36 [PATCH v10 00/61] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 01/61] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 02/61] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 03/61] target/riscv: support vector extension csr LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 04/61] target/riscv: add vector configure instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 05/61] target/riscv: add an internals.h header LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 06/61] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-06-23 16:52 ` Alistair Francis
2020-06-23 21:32 ` LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 07/61] target/riscv: add vector index " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 08/61] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 09/61] target/riscv: add vector amo operations LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 10/61] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 11/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 13/61] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 14/61] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 15/61] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 16/61] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 17/61] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 18/61] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 19/61] target/riscv: vector integer divide instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 20/61] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 21/61] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 22/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 23/61] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 24/61] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 25/61] target/riscv: vector single-width averaging " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 27/61] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 28/61] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 29/61] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 30/61] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 31/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 32/61] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 33/61] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 35/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 36/61] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 37/61] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 38/61] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 39/61] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 40/61] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 41/61] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-06-20 4:36 ` LIU Zhiwei [this message]
2020-06-20 4:36 ` [PATCH v10 43/61] target/riscv: widening floating-point/integer type-convert instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 44/61] target/riscv: narrowing " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 45/61] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 46/61] target/riscv: vector wideing " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 47/61] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 48/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 49/61] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 50/61] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 51/61] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 52/61] target/riscv: set-X-first " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 53/61] target/riscv: vector iota instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 54/61] target/riscv: vector element index instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 55/61] target/riscv: integer extract instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 56/61] target/riscv: integer scalar move instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 57/61] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 58/61] target/riscv: vector slide instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 59/61] target/riscv: vector register gather instruction LIU Zhiwei
2020-06-20 4:37 ` [PATCH v10 60/61] target/riscv: vector compress instruction LIU Zhiwei
2020-06-20 4:37 ` [PATCH v10 61/61] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
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