From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: richard.henderson@linaro.org, wxy194768@alibaba-inc.com,
wenmeng_zhang@c-sky.com,
Alistair Francis <alistair.francis@wdc.com>,
palmer@dabbelt.com, LIU Zhiwei <zhiwei_liu@c-sky.com>
Subject: [PATCH v10 48/61] target/riscv: vector widening floating-point reduction instructions
Date: Sat, 20 Jun 2020 12:36:48 +0800 [thread overview]
Message-ID: <20200620043701.1323-49-zhiwei_liu@c-sky.com> (raw)
In-Reply-To: <20200620043701.1323-1-zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/helper.h | 3 ++
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvv.inc.c | 3 ++
target/riscv/vector_helper.c | 46 +++++++++++++++++++++++++
4 files changed, 54 insertions(+)
diff --git a/target/riscv/helper.h b/target/riscv/helper.h
index 8e8b8d0407..217f09a55c 100644
--- a/target/riscv/helper.h
+++ b/target/riscv/helper.h
@@ -1089,3 +1089,6 @@ DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 986308e99a..2668d483a7 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -545,6 +545,8 @@ vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm
vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
+# Vector widening ordered and unordered float reduction sum
+vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.inc.c
index 7e9d0ded37..1f1559b0bd 100644
--- a/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2351,3 +2351,6 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
GEN_OPFVV_TRANS(vfredsum_vs, reduction_check)
GEN_OPFVV_TRANS(vfredmax_vs, reduction_check)
GEN_OPFVV_TRANS(vfredmin_vs, reduction_check)
+
+/* Vector Widening Floating-Point Reduction Instructions */
+GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index ba961230f6..e30f8f83d3 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -4456,3 +4456,49 @@ GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8, H8, float64_maxnum, clearq)
GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum, clearh)
GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum, clearl)
GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, clearq)
+
+/* Vector Widening Floating-Point Reduction Instructions */
+/* Unordered reduce 2*SEW = 2*SEW + sum(promote(SEW)) */
+void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1,
+ void *vs2, CPURISCVState *env, uint32_t desc)
+{
+ uint32_t mlen = vext_mlen(desc);
+ uint32_t vm = vext_vm(desc);
+ uint32_t vl = env->vl;
+ uint32_t i;
+ uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
+ uint32_t s1 = *((uint32_t *)vs1 + H4(0));
+
+ for (i = 0; i < vl; i++) {
+ uint16_t s2 = *((uint16_t *)vs2 + H2(i));
+ if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ continue;
+ }
+ s1 = float32_add(s1, float16_to_float32(s2, true, &env->fp_status),
+ &env->fp_status);
+ }
+ *((uint32_t *)vd + H4(0)) = s1;
+ clearl(vd, 1, sizeof(uint32_t), tot);
+}
+
+void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1,
+ void *vs2, CPURISCVState *env, uint32_t desc)
+{
+ uint32_t mlen = vext_mlen(desc);
+ uint32_t vm = vext_vm(desc);
+ uint32_t vl = env->vl;
+ uint32_t i;
+ uint32_t tot = env_archcpu(env)->cfg.vlen / 8;
+ uint64_t s1 = *((uint64_t *)vs1);
+
+ for (i = 0; i < vl; i++) {
+ uint32_t s2 = *((uint32_t *)vs2 + H4(i));
+ if (!vm && !vext_elem_mask(v0, mlen, i)) {
+ continue;
+ }
+ s1 = float64_add(s1, float32_to_float64(s2, &env->fp_status),
+ &env->fp_status);
+ }
+ *((uint64_t *)vd) = s1;
+ clearq(vd, 1, sizeof(uint64_t), tot);
+}
--
2.23.0
next prev parent reply other threads:[~2020-06-20 6:14 UTC|newest]
Thread overview: 64+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-20 4:36 [PATCH v10 00/61] target/riscv: support vector extension v0.7.1 LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 01/61] target/riscv: add vector extension field in CPURISCVState LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 02/61] target/riscv: implementation-defined constant parameters LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 03/61] target/riscv: support vector extension csr LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 04/61] target/riscv: add vector configure instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 05/61] target/riscv: add an internals.h header LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 06/61] target/riscv: add vector stride load and store instructions LIU Zhiwei
2020-06-23 16:52 ` Alistair Francis
2020-06-23 21:32 ` LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 07/61] target/riscv: add vector index " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 08/61] target/riscv: add fault-only-first unit stride load LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 09/61] target/riscv: add vector amo operations LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 10/61] target/riscv: vector single-width integer add and subtract LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 11/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 12/61] target/riscv: vector integer add-with-carry / subtract-with-borrow instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 13/61] target/riscv: vector bitwise logical instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 14/61] target/riscv: vector single-width bit shift instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 15/61] target/riscv: vector narrowing integer right " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 16/61] target/riscv: vector integer comparison instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 17/61] target/riscv: vector integer min/max instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 18/61] target/riscv: vector single-width integer multiply instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 19/61] target/riscv: vector integer divide instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 20/61] target/riscv: vector widening integer multiply instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 21/61] target/riscv: vector single-width integer multiply-add instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 22/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 23/61] target/riscv: vector integer merge and move instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 24/61] target/riscv: vector single-width saturating add and subtract LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 25/61] target/riscv: vector single-width averaging " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 26/61] target/riscv: vector single-width fractional multiply with rounding and saturation LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 27/61] target/riscv: vector widening saturating scaled multiply-add LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 28/61] target/riscv: vector single-width scaling shift instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 29/61] target/riscv: vector narrowing fixed-point clip instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 30/61] target/riscv: vector single-width floating-point add/subtract instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 31/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 32/61] target/riscv: vector single-width floating-point multiply/divide instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 33/61] target/riscv: vector widening floating-point multiply LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 34/61] target/riscv: vector single-width floating-point fused multiply-add instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 35/61] target/riscv: vector widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 36/61] target/riscv: vector floating-point square-root instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 37/61] target/riscv: vector floating-point min/max instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 38/61] target/riscv: vector floating-point sign-injection instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 39/61] target/riscv: vector floating-point compare instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 40/61] target/riscv: vector floating-point classify instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 41/61] target/riscv: vector floating-point merge instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 42/61] target/riscv: vector floating-point/integer type-convert instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 43/61] target/riscv: widening " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 44/61] target/riscv: narrowing " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 45/61] target/riscv: vector single-width integer reduction instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 46/61] target/riscv: vector wideing " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 47/61] target/riscv: vector single-width floating-point " LIU Zhiwei
2020-06-20 4:36 ` LIU Zhiwei [this message]
2020-06-20 4:36 ` [PATCH v10 49/61] target/riscv: vector mask-register logical instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 50/61] target/riscv: vector mask population count vmpopc LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 51/61] target/riscv: vmfirst find-first-set mask bit LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 52/61] target/riscv: set-X-first " LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 53/61] target/riscv: vector iota instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 54/61] target/riscv: vector element index instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 55/61] target/riscv: integer extract instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 56/61] target/riscv: integer scalar move instruction LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 57/61] target/riscv: floating-point scalar move instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 58/61] target/riscv: vector slide instructions LIU Zhiwei
2020-06-20 4:36 ` [PATCH v10 59/61] target/riscv: vector register gather instruction LIU Zhiwei
2020-06-20 4:37 ` [PATCH v10 60/61] target/riscv: vector compress instruction LIU Zhiwei
2020-06-20 4:37 ` [PATCH v10 61/61] target/riscv: configure and turn on vector extension from command line LIU Zhiwei
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