From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org,
david.spickett@linaro.org, steplong@quicinc.com
Subject: [PATCH v8 07/45] target/arm: Add MTE system registers
Date: Tue, 23 Jun 2020 12:36:20 -0700 [thread overview]
Message-ID: <20200623193658.623279-8-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200623193658.623279-1-richard.henderson@linaro.org>
This is TFSRE0_EL1, TFSR_EL1, TFSR_EL2, TFSR_EL3,
RGSR_EL1, GCR_EL1, GMID_EL1, and PSTATE.TCO.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Add GMID; add access_mte.
v4: Define only TCO at mte_insn_reg.
v6: Define RAZ/WI version of TCO at mte_insn_reg;
honor TID5 for GMID_EL1; fix TFS crn/crm; recalc hflags after TCO.
---
target/arm/cpu.h | 4 ++
target/arm/internals.h | 9 ++++
target/arm/helper.c | 94 ++++++++++++++++++++++++++++++++++++++
target/arm/translate-a64.c | 21 +++++++++
4 files changed, 128 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index f8ac11e73b..49cf37d43b 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -502,6 +502,9 @@ typedef struct CPUARMState {
uint64_t pmccfiltr_el0; /* Performance Monitor Filter Register */
uint64_t vpidr_el2; /* Virtualization Processor ID Register */
uint64_t vmpidr_el2; /* Virtualization Multiprocessor ID Register */
+ uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */
+ uint64_t gcr_el1;
+ uint64_t rgsr_el1;
} cp15;
struct {
@@ -1282,6 +1285,7 @@ void pmu_init(ARMCPU *cpu);
#define PSTATE_SS (1U << 21)
#define PSTATE_PAN (1U << 22)
#define PSTATE_UAO (1U << 23)
+#define PSTATE_TCO (1U << 25)
#define PSTATE_V (1U << 28)
#define PSTATE_C (1U << 29)
#define PSTATE_Z (1U << 30)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 4bdbc3a8ac..56b4672685 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1159,6 +1159,9 @@ static inline uint32_t aarch64_pstate_valid_mask(const ARMISARegisters *id)
if (isar_feature_aa64_uao(id)) {
valid |= PSTATE_UAO;
}
+ if (isar_feature_aa64_mte(id)) {
+ valid |= PSTATE_TCO;
+ }
return valid;
}
@@ -1234,4 +1237,10 @@ void arm_log_exception(int idx);
#endif /* !CONFIG_USER_ONLY */
+/*
+ * The log2 of the words in the tag block, for GMID_EL1.BS.
+ * The is the maximum, 256 bytes, which manipulates 64-bits of tags.
+ */
+#define GMID_EL1_BS 6
+
#endif
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d6c326b58e..b4842ea23e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5881,6 +5881,9 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu)
{ K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0),
"ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve },
+ { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0),
+ "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte },
+
/* TODO: ARMv8.2-SPE -- PMSCR_EL2 */
/* TODO: ARMv8.4-Trace -- TRFCR_EL2 */
};
@@ -6855,6 +6858,86 @@ static const ARMCPRegInfo dcpodp_reg[] = {
};
#endif /*CONFIG_USER_ONLY*/
+static CPAccessResult access_aa64_tid5(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID5)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+
+ return CP_ACCESS_OK;
+}
+
+static CPAccessResult access_mte(CPUARMState *env, const ARMCPRegInfo *ri,
+ bool isread)
+{
+ int el = arm_current_el(env);
+
+ if (el < 2 &&
+ arm_feature(env, ARM_FEATURE_EL2) &&
+ !(arm_hcr_el2_eff(env) & HCR_ATA)) {
+ return CP_ACCESS_TRAP_EL2;
+ }
+ if (el < 3 &&
+ arm_feature(env, ARM_FEATURE_EL3) &&
+ !(env->cp15.scr_el3 & SCR_ATA)) {
+ return CP_ACCESS_TRAP_EL3;
+ }
+ return CP_ACCESS_OK;
+}
+
+static uint64_t tco_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ return env->pstate & PSTATE_TCO;
+}
+
+static void tco_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
+{
+ env->pstate = (env->pstate & ~PSTATE_TCO) | (val & PSTATE_TCO);
+}
+
+static const ARMCPRegInfo mte_reginfo[] = {
+ { .name = "TFSRE0_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 1,
+ .access = PL1_RW, .accessfn = access_mte,
+ .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[0]) },
+ { .name = "TFSR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 6, .opc2 = 0,
+ .access = PL1_RW, .accessfn = access_mte,
+ .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[1]) },
+ { .name = "TFSR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 5, .crm = 6, .opc2 = 0,
+ .access = PL2_RW, .accessfn = access_mte,
+ .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[2]) },
+ { .name = "TFSR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 5, .crm = 6, .opc2 = 0,
+ .access = PL3_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.tfsr_el[3]) },
+ { .name = "RGSR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 5,
+ .access = PL1_RW, .accessfn = access_mte,
+ .fieldoffset = offsetof(CPUARMState, cp15.rgsr_el1) },
+ { .name = "GCR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 6,
+ .access = PL1_RW, .accessfn = access_mte,
+ .fieldoffset = offsetof(CPUARMState, cp15.gcr_el1) },
+ { .name = "GMID_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 4,
+ .access = PL1_R, .accessfn = access_aa64_tid5,
+ .type = ARM_CP_CONST, .resetvalue = GMID_EL1_BS },
+ { .name = "TCO", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
+ .type = ARM_CP_NO_RAW,
+ .access = PL0_RW, .readfn = tco_read, .writefn = tco_write },
+ REGINFO_SENTINEL
+};
+
+static const ARMCPRegInfo mte_tco_ro_reginfo[] = {
+ { .name = "TCO", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .crn = 4, .crm = 2, .opc2 = 7,
+ .type = ARM_CP_CONST, .access = PL0_RW, },
+ REGINFO_SENTINEL
+};
#endif
static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo *ri,
@@ -7980,6 +8063,17 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
}
#endif /*CONFIG_USER_ONLY*/
+
+ /*
+ * If full MTE is enabled, add all of the system registers.
+ * If only "instructions available at EL0" are enabled,
+ * then define only a RAZ/WI version of PSTATE.TCO.
+ */
+ if (cpu_isar_feature(aa64_mte, cpu)) {
+ define_arm_cp_regs(cpu, mte_reginfo);
+ } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) {
+ define_arm_cp_regs(cpu, mte_tco_ro_reginfo);
+ }
#endif
if (cpu_isar_feature(any_predinv, cpu)) {
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b4bf4cce18..efdfd50fb6 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1619,6 +1619,27 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
s->base.is_jmp = DISAS_UPDATE_EXIT;
break;
+ case 0x1c: /* TCO */
+ if (dc_isar_feature(aa64_mte, s)) {
+ /* Full MTE is enabled -- set the TCO bit as directed. */
+ if (crm & 1) {
+ set_pstate_bits(PSTATE_TCO);
+ } else {
+ clear_pstate_bits(PSTATE_TCO);
+ }
+ t1 = tcg_const_i32(s->current_el);
+ gen_helper_rebuild_hflags_a64(cpu_env, t1);
+ tcg_temp_free_i32(t1);
+ /* Many factors, including TCO, go into MTE_ACTIVE. */
+ s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
+ } else if (dc_isar_feature(aa64_mte_insn_reg, s)) {
+ /* Only "instructions accessible at EL0" -- PSTATE.TCO is WI. */
+ s->base.is_jmp = DISAS_NEXT;
+ } else {
+ goto do_unallocated;
+ }
+ break;
+
default:
do_unallocated:
unallocated_encoding(s);
--
2.25.1
next prev parent reply other threads:[~2020-06-23 19:38 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-06-23 19:36 [PATCH v8 00/45] target/arm: Implement ARMv8.5-MemTag, system mode Richard Henderson
2020-06-23 19:36 ` [PATCH v8 01/45] target/arm: Add isar tests for mte Richard Henderson
2020-06-23 19:36 ` [PATCH v8 02/45] target/arm: Improve masking of SCR RES0 bits Richard Henderson
2020-06-23 19:36 ` [PATCH v8 03/45] target/arm: Add support for MTE to SCTLR_ELx Richard Henderson
2020-06-23 19:36 ` [PATCH v8 04/45] target/arm: Add support for MTE to HCR_EL2 and SCR_EL3 Richard Henderson
2020-06-23 19:36 ` [PATCH v8 05/45] target/arm: Rename DISAS_UPDATE to DISAS_UPDATE_EXIT Richard Henderson
2020-06-23 19:36 ` [PATCH v8 06/45] target/arm: Add DISAS_UPDATE_NOCHAIN Richard Henderson
2020-06-23 19:36 ` Richard Henderson [this message]
2020-06-23 19:36 ` [PATCH v8 08/45] target/arm: Add MTE bits to tb_flags Richard Henderson
2020-06-23 19:36 ` [PATCH v8 09/45] target/arm: Implement the IRG instruction Richard Henderson
2020-06-23 19:36 ` [PATCH v8 10/45] target/arm: Revise decoding for disas_add_sub_imm Richard Henderson
2020-06-25 10:16 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 11/45] target/arm: Implement the ADDG, SUBG instructions Richard Henderson
2020-06-25 10:39 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 12/45] target/arm: Implement the GMI instruction Richard Henderson
2020-06-23 19:36 ` [PATCH v8 13/45] target/arm: Implement the SUBP instruction Richard Henderson
2020-06-23 19:36 ` [PATCH v8 14/45] target/arm: Define arm_cpu_do_unaligned_access for user-only Richard Henderson
2020-06-25 10:45 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 15/45] target/arm: Implement LDG, STG, ST2G instructions Richard Henderson
2020-06-25 10:48 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 16/45] target/arm: Implement the STGP instruction Richard Henderson
2020-06-23 19:36 ` [PATCH v8 17/45] target/arm: Restrict the values of DCZID.BS under TCG Richard Henderson
2020-06-23 19:36 ` [PATCH v8 18/45] target/arm: Simplify DC_ZVA Richard Henderson
2020-06-23 19:36 ` [PATCH v8 19/45] target/arm: Implement the LDGM, STGM, STZGM instructions Richard Henderson
2020-06-23 19:36 ` [PATCH v8 20/45] target/arm: Implement the access tag cache flushes Richard Henderson
2020-06-23 19:36 ` [PATCH v8 21/45] target/arm: Move regime_el to internals.h Richard Henderson
2020-06-23 19:36 ` [PATCH v8 22/45] target/arm: Move regime_tcr " Richard Henderson
2020-06-23 19:36 ` [PATCH v8 23/45] target/arm: Add gen_mte_check1 Richard Henderson
2020-06-23 19:36 ` [PATCH v8 24/45] target/arm: Add gen_mte_checkN Richard Henderson
2020-06-23 19:36 ` [PATCH v8 25/45] target/arm: Implement helper_mte_check1 Richard Henderson
2020-06-25 10:55 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 26/45] target/arm: Implement helper_mte_checkN Richard Henderson
2020-06-23 19:36 ` [PATCH v8 27/45] target/arm: Add helper_mte_check_zva Richard Henderson
2020-06-23 19:36 ` [PATCH v8 28/45] target/arm: Use mte_checkN for sve unpredicated loads Richard Henderson
2020-06-25 11:06 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 29/45] target/arm: Use mte_checkN for sve unpredicated stores Richard Henderson
2020-06-25 11:07 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 30/45] target/arm: Use mte_check1 for sve LD1R Richard Henderson
2020-06-25 11:12 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 31/45] target/arm: Tidy trans_LD1R_zpri Richard Henderson
2020-06-25 11:12 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 32/45] target/arm: Add arm_tlb_bti_gp Richard Henderson
2020-06-25 12:29 ` Peter Maydell
2020-06-25 18:59 ` Richard Henderson
2020-06-23 19:36 ` [PATCH v8 33/45] target/arm: Add mte helpers for sve scalar + int loads Richard Henderson
2020-06-25 12:36 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 34/45] target/arm: Add mte helpers for sve scalar + int stores Richard Henderson
2020-06-25 12:37 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 35/45] target/arm: Add mte helpers for sve scalar + int ff/nf loads Richard Henderson
2020-06-25 12:38 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 36/45] target/arm: Handle TBI for sve scalar + int memory ops Richard Henderson
2020-06-25 12:40 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 37/45] target/arm: Add mte helpers for sve scatter/gather " Richard Henderson
2020-06-25 12:43 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 38/45] target/arm: Complete TBI clearing for user-only for SVE Richard Henderson
2020-06-25 12:52 ` Peter Maydell
2020-06-25 16:54 ` Richard Henderson
2020-06-25 17:07 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 39/45] target/arm: Implement data cache set allocation tags Richard Henderson
2020-06-23 19:36 ` [PATCH v8 40/45] target/arm: Set PSTATE.TCO on exception entry Richard Henderson
2020-06-23 19:36 ` [PATCH v8 41/45] target/arm: Always pass cacheattr to get_phys_addr Richard Henderson
2020-06-25 12:56 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 42/45] target/arm: Cache the Tagged bit for a page in MemTxAttrs Richard Henderson
2020-06-25 12:59 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 43/45] target/arm: Create tagged ram when MTE is enabled Richard Henderson
2020-06-25 13:26 ` Peter Maydell
2020-06-23 19:36 ` [PATCH v8 44/45] target/arm: Add allocation tag storage for system mode Richard Henderson
2020-06-25 13:03 ` Peter Maydell
2020-06-25 17:02 ` Richard Henderson
2020-06-25 17:09 ` Peter Maydell
2020-06-25 22:16 ` Richard Henderson
2020-06-23 19:36 ` [PATCH v8 45/45] target/arm: Enable MTE Richard Henderson
2020-06-25 13:06 ` Peter Maydell
2020-06-23 19:55 ` [PATCH v8 00/45] target/arm: Implement ARMv8.5-MemTag, system mode Derrick McKee
2020-06-23 20:06 ` Richard Henderson
2020-06-23 20:30 ` no-reply
2020-06-25 13:28 ` Peter Maydell
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