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25 Jun 2020 17:21:44 -0700 IronPort-SDR: qQRJJ2loKD4Nn+WRm58D/S5rlnAsWb5Mqz0pv7PzNkr3JN3qtiEu6gNFViAqlE6LnbitUyfyl6 qBC2Go6HGIVQ== WDCIronportException: Internal Received: from usa003490.ad.shared (HELO yoda.hgst.com) ([10.86.58.205]) by uls-op-cesaip01.wdc.com with ESMTP; 25 Jun 2020 17:33:17 -0700 From: Atish Patra To: qemu-devel@nongnu.org Subject: [PATCH v3 1/3] riscv: Unify Qemu's reset vector code path Date: Thu, 25 Jun 2020 17:33:11 -0700 Message-Id: <20200626003313.715355-2-atish.patra@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200626003313.715355-1-atish.patra@wdc.com> References: <20200626003313.715355-1-atish.patra@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=4399c1bdf=atish.patra@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/25 20:33:16 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Sagar Karandikar , Bastian Koppelmann , Atish Patra , Alistair Francis , Alexander Richardson , Palmer Dabbelt , Bin Meng Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Currently, all riscv machines except sifive_u have identical reset vector code implementations with memory addresses being different for all machines. They can be easily combined into a single function in common code. Move it to common function and let all the machines use the common function. Signed-off-by: Atish Patra Reviewed-by: Alistair Francis --- hw/riscv/boot.c | 45 +++++++++++++++++++++++++++++++++++++++++ hw/riscv/sifive_u.c | 1 - hw/riscv/spike.c | 41 +++---------------------------------- hw/riscv/virt.c | 40 +++--------------------------------- include/hw/riscv/boot.h | 2 ++ 5 files changed, 53 insertions(+), 76 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index adb421b91b68..482b78147993 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -26,8 +26,11 @@ #include "hw/loader.h" #include "hw/riscv/boot.h" #include "elf.h" +#include "sysemu/device_tree.h" #include "sysemu/qtest.h" +#include + #if defined(TARGET_RISCV32) # define KERNEL_BOOT_ADDRESS 0x80400000 #else @@ -155,3 +158,45 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, return *start + size; } + +void riscv_setup_rom_reset_vec(hwaddr start_addr, hwaddr rom_base, + hwaddr rom_size, void *fdt) +{ + int i; + /* reset vector */ + uint32_t reset_vec[8] = { + 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ + 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ + 0xf1402573, /* csrr a0, mhartid */ +#if defined(TARGET_RISCV32) + 0x0182a283, /* lw t0, 24(t0) */ +#elif defined(TARGET_RISCV64) + 0x0182b283, /* ld t0, 24(t0) */ +#endif + 0x00028067, /* jr t0 */ + 0x00000000, + start_addr, /* start: .dword */ + 0x00000000, + /* dtb: */ + }; + + /* copy in the reset vector in little_endian byte order */ + for (i = 0; i < sizeof(reset_vec) >> 2; i++) { + reset_vec[i] = cpu_to_le32(reset_vec[i]); + } + rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), + rom_base, &address_space_memory); + + /* copy in the device tree */ + if (fdt_pack(fdt) || fdt_totalsize(fdt) > + rom_size - sizeof(reset_vec)) { + error_report("not enough space to store device-tree"); + exit(1); + } + qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); + rom_add_blob_fixed_as("mrom.fdt", fdt, fdt_totalsize(fdt), + rom_base + sizeof(reset_vec), + &address_space_memory); + + return; +} diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7d051e7c9299..395b21703ab4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -56,7 +56,6 @@ #include "sysemu/device_tree.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" #include diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 3c87e04fdceb..c696077cbc16 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -41,9 +41,6 @@ #include "sysemu/device_tree.h" #include "sysemu/qtest.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" - -#include #if defined(TARGET_RISCV32) # define BIOS_FILENAME "opensbi-riscv32-spike-fw_jump.elf" @@ -165,7 +162,6 @@ static void spike_board_init(MachineState *machine) MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); MemoryRegion *mask_rom = g_new(MemoryRegion, 1); - int i; unsigned int smp_cpus = machine->smp.cpus; /* Initialize SOC */ @@ -212,40 +208,9 @@ static void spike_board_init(MachineState *machine) } } - /* reset vector */ - uint32_t reset_vec[8] = { - 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ - 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ - 0xf1402573, /* csrr a0, mhartid */ -#if defined(TARGET_RISCV32) - 0x0182a283, /* lw t0, 24(t0) */ -#elif defined(TARGET_RISCV64) - 0x0182b283, /* ld t0, 24(t0) */ -#endif - 0x00028067, /* jr t0 */ - 0x00000000, - memmap[SPIKE_DRAM].base, /* start: .dword DRAM_BASE */ - 0x00000000, - /* dtb: */ - }; - - /* copy in the reset vector in little_endian byte order */ - for (i = 0; i < sizeof(reset_vec) >> 2; i++) { - reset_vec[i] = cpu_to_le32(reset_vec[i]); - } - rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), - memmap[SPIKE_MROM].base, &address_space_memory); - - /* copy in the device tree */ - if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > - memmap[SPIKE_MROM].size - sizeof(reset_vec)) { - error_report("not enough space to store device-tree"); - exit(1); - } - qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); - rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), - memmap[SPIKE_MROM].base + sizeof(reset_vec), - &address_space_memory); + /* load the reset vector */ + riscv_setup_rom_reset_vec(memmap[SPIKE_DRAM].base, memmap[SPIKE_MROM].base, + memmap[SPIKE_MROM].size, s->fdt); /* initialize HTIF using symbols found in load_kernel */ htif_mm_init(system_memory, mask_rom, &s->soc.harts[0].env, serial_hd(0)); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 616db6f5aced..8ec77e43de26 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -39,12 +39,9 @@ #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" -#include - #if defined(TARGET_RISCV32) # define BIOS_FILENAME "opensbi-riscv32-virt-fw_jump.bin" #else @@ -535,40 +532,9 @@ static void virt_machine_init(MachineState *machine) start_addr = virt_memmap[VIRT_FLASH].base; } - /* reset vector */ - uint32_t reset_vec[8] = { - 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ - 0x02028593, /* addi a1, t0, %pcrel_lo(1b) */ - 0xf1402573, /* csrr a0, mhartid */ -#if defined(TARGET_RISCV32) - 0x0182a283, /* lw t0, 24(t0) */ -#elif defined(TARGET_RISCV64) - 0x0182b283, /* ld t0, 24(t0) */ -#endif - 0x00028067, /* jr t0 */ - 0x00000000, - start_addr, /* start: .dword */ - 0x00000000, - /* dtb: */ - }; - - /* copy in the reset vector in little_endian byte order */ - for (i = 0; i < sizeof(reset_vec) >> 2; i++) { - reset_vec[i] = cpu_to_le32(reset_vec[i]); - } - rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), - memmap[VIRT_MROM].base, &address_space_memory); - - /* copy in the device tree */ - if (fdt_pack(s->fdt) || fdt_totalsize(s->fdt) > - memmap[VIRT_MROM].size - sizeof(reset_vec)) { - error_report("not enough space to store device-tree"); - exit(1); - } - qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); - rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), - memmap[VIRT_MROM].base + sizeof(reset_vec), - &address_space_memory); + /* load the reset vector */ + riscv_setup_rom_reset_vec(start_addr, virt_memmap[VIRT_MROM].base, + virt_memmap[VIRT_MROM].size, s->fdt); /* create PLIC hart topology configuration string */ plic_hart_config_len = (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpus; diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 9daa98da08d7..3e9759c89aa2 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -35,5 +35,7 @@ target_ulong riscv_load_kernel(const char *kernel_filename, symbol_fn_t sym_cb); hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, uint64_t kernel_entry, hwaddr *start); +void riscv_setup_rom_reset_vec(hwaddr saddr, hwaddr rom_base, + hwaddr rom_size, void *fdt); #endif /* RISCV_BOOT_H */ -- 2.26.2