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[79.182.31.92]) by smtp.gmail.com with ESMTPSA id u23sm7551973wru.94.2020.07.01.05.01.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Jul 2020 05:01:57 -0700 (PDT) Date: Wed, 1 Jul 2020 08:01:55 -0400 From: "Michael S. Tsirkin" To: Anthony PERARD Subject: Re: [PATCH] acpi: Fix access to PM1 control and status registers Message-ID: <20200701075914-mutt-send-email-mst@kernel.org> References: <20200701110549.148522-1-anthony.perard@citrix.com> MIME-Version: 1.0 In-Reply-To: <20200701110549.148522-1-anthony.perard@citrix.com> Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=mst@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=205.139.110.120; envelope-from=mst@redhat.com; helo=us-smtp-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/30 22:25:53 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Igor Mammedov , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Wed, Jul 01, 2020 at 12:05:49PM +0100, Anthony PERARD wrote: > The ACPI spec state that "Accesses to PM1 control registers are > accessed through byte and word accesses." (In section 4.7.3.2.1 PM1 > Control Registers of my old spec copy rev 4.0a). > > With commit 5d971f9e6725 ("memory: Revert "memory: accept mismatching > sizes in memory_region_access_valid""), it wasn't possible anymore to > access the pm1_cnt register by reading a single byte, and that is use > by at least a Xen firmware called "hvmloader". > > Also, take care of the PM1 Status Registers which also have "Accesses > to the PM1 status registers are done through byte or word accesses" > (In section 4.7.3.1.1 PM1 Status Registers). > > Signed-off-by: Anthony PERARD Can't we set impl.min_access_size to convert byte accesses to word accesses? > --- > hw/acpi/core.c | 46 +++++++++++++++++++++++++++++++++++++--------- > 1 file changed, 37 insertions(+), 9 deletions(-) > > diff --git a/hw/acpi/core.c b/hw/acpi/core.c > index 45cbed49abdd..31974e2f91bf 100644 > --- a/hw/acpi/core.c > +++ b/hw/acpi/core.c > @@ -394,9 +394,17 @@ uint16_t acpi_pm1_evt_get_sts(ACPIREGS *ar) > return ar->pm1.evt.sts; > } > > -static void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint16_t val) > +static void acpi_pm1_evt_write_sts(ACPIREGS *ar, hwaddr addr, uint16_t val, > + unsigned width) > { > uint16_t pm1_sts = acpi_pm1_evt_get_sts(ar); > + if (width == 1) { > + if (addr == 0) { > + val |= pm1_sts & 0xff00; > + } else if (addr == 1) { > + val = (val << BITS_PER_BYTE) | (pm1_sts & 0xff); > + } > + } > if (pm1_sts & val & ACPI_BITMASK_TIMER_STATUS) { > /* if TMRSTS is reset, then compute the new overflow time */ > acpi_pm_tmr_calc_overflow_time(ar); > @@ -404,8 +412,16 @@ static void acpi_pm1_evt_write_sts(ACPIREGS *ar, uint16_t val) > ar->pm1.evt.sts &= ~val; > } > > -static void acpi_pm1_evt_write_en(ACPIREGS *ar, uint16_t val) > +static void acpi_pm1_evt_write_en(ACPIREGS *ar, hwaddr addr, uint16_t val, > + unsigned width) > { > + if (width == 1) { > + if (addr == 0) { > + val |= ar->pm1.evt.en & 0xff00; > + } else if (addr == 1) { > + val = (val << BITS_PER_BYTE) | (ar->pm1.evt.en & 0xff); > + } > + } > ar->pm1.evt.en = val; > qemu_system_wakeup_enable(QEMU_WAKEUP_REASON_RTC, > val & ACPI_BITMASK_RT_CLOCK_ENABLE); > @@ -434,9 +450,11 @@ static uint64_t acpi_pm_evt_read(void *opaque, hwaddr addr, unsigned width) > ACPIREGS *ar = opaque; > switch (addr) { > case 0: > - return acpi_pm1_evt_get_sts(ar); > + case 1: > + return acpi_pm1_evt_get_sts(ar) >> (addr * BITS_PER_BYTE); > case 2: > - return ar->pm1.evt.en; > + case 3: > + return ar->pm1.evt.en >> ((addr - 2) * BITS_PER_BYTE); > default: > return 0; > } > @@ -448,11 +466,13 @@ static void acpi_pm_evt_write(void *opaque, hwaddr addr, uint64_t val, > ACPIREGS *ar = opaque; > switch (addr) { > case 0: > - acpi_pm1_evt_write_sts(ar, val); > + case 1: > + acpi_pm1_evt_write_sts(ar, addr, val, width); > ar->pm1.evt.update_sci(ar); > break; > case 2: > - acpi_pm1_evt_write_en(ar, val); > + case 3: > + acpi_pm1_evt_write_en(ar, addr - 2, val, width); > ar->pm1.evt.update_sci(ar); > break; > } > @@ -461,7 +481,7 @@ static void acpi_pm_evt_write(void *opaque, hwaddr addr, uint64_t val, > static const MemoryRegionOps acpi_pm_evt_ops = { > .read = acpi_pm_evt_read, > .write = acpi_pm_evt_write, > - .valid.min_access_size = 2, > + .valid.min_access_size = 1, > .valid.max_access_size = 2, > .endianness = DEVICE_LITTLE_ENDIAN, > }; > @@ -590,19 +610,27 @@ void acpi_pm1_cnt_update(ACPIREGS *ar, > static uint64_t acpi_pm_cnt_read(void *opaque, hwaddr addr, unsigned width) > { > ACPIREGS *ar = opaque; > - return ar->pm1.cnt.cnt; > + return ar->pm1.cnt.cnt >> (addr * BITS_PER_BYTE); > } > > static void acpi_pm_cnt_write(void *opaque, hwaddr addr, uint64_t val, > unsigned width) > { > + ACPIREGS *ar = opaque; > + if (width == 1) { > + if (addr == 0) { > + val |= ar->pm1.cnt.cnt & 0xff00; > + } else if (addr == 1) { > + val = (val << BITS_PER_BYTE) | (ar->pm1.cnt.cnt & 0xff); > + } > + } > acpi_pm1_cnt_write(opaque, val); > } > > static const MemoryRegionOps acpi_pm_cnt_ops = { > .read = acpi_pm_cnt_read, > .write = acpi_pm_cnt_write, > - .valid.min_access_size = 2, > + .valid.min_access_size = 1, > .valid.max_access_size = 2, > .endianness = DEVICE_LITTLE_ENDIAN, > }; > -- > Anthony PERARD