From: Lijun Pan <ljp@linux.ibm.com>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: Lijun Pan <ljp@linux.ibm.com>,
richard.henderson@linaro.org, david@gibson.dropbear.id.au
Subject: [PATCH v4 09/11] fix the prototype of muls64/mulu64
Date: Wed, 1 Jul 2020 18:43:44 -0500 [thread overview]
Message-ID: <20200701234344.91843-10-ljp@linux.ibm.com> (raw)
In-Reply-To: <20200701234344.91843-1-ljp@linux.ibm.com>
The prototypes of muls64/mulu64 in host-utils.h should match the
definitions in host-utils.c
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
no change since v1
include/qemu/host-utils.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index 4cd170e6cd..cdca2991d8 100644
--- a/include/qemu/host-utils.h
+++ b/include/qemu/host-utils.h
@@ -77,8 +77,8 @@ static inline int divs128(int64_t *plow, int64_t *phigh, int64_t divisor)
}
}
#else
-void muls64(uint64_t *phigh, uint64_t *plow, int64_t a, int64_t b);
-void mulu64(uint64_t *phigh, uint64_t *plow, uint64_t a, uint64_t b);
+void muls64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b);
+void mulu64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b);
int divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor);
int divs128(int64_t *plow, int64_t *phigh, int64_t divisor);
--
2.23.0
next prev parent reply other threads:[~2020-07-01 23:49 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-01 23:43 [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
2020-07-01 23:43 ` [PATCH v4 01/11] target/ppc: Introduce Power ISA 3.1 flag Lijun Pan
2020-07-05 9:07 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 02/11] target/ppc: Enable Power ISA 3.1 Lijun Pan
2020-07-05 9:08 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 03/11] target/ppc: add byte-reverse br[dwh] instructions Lijun Pan
2020-07-07 10:30 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 04/11] target/ppc: convert vmuluwm to tcg_gen_gvec_mul Lijun Pan
2020-07-08 12:22 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 05/11] target/ppc: add vmulld instruction Lijun Pan
2020-07-13 5:11 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition Lijun Pan
2020-07-13 5:14 ` David Gibson
2020-07-13 19:20 ` Lijun Pan
2020-07-13 23:47 ` David Gibson
2020-07-14 20:28 ` Lijun Pan
2020-07-01 23:43 ` [PATCH v4 07/11] target/ppc: add vmulld to INDEX_op_mul_vec case Lijun Pan
2020-07-13 19:40 ` Lijun Pan
2020-07-01 23:43 ` [PATCH v4 08/11] target/ppc: add vmulh{su}w instructions Lijun Pan
2020-07-13 19:35 ` Lijun Pan
2020-07-01 23:43 ` Lijun Pan [this message]
2020-07-06 16:14 ` [PATCH v4 09/11] fix the prototype of muls64/mulu64 Laurent Vivier
2020-07-05 9:10 ` [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions David Gibson
2020-07-06 7:34 ` Greg Kurz
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200701234344.91843-10-ljp@linux.ibm.com \
--to=ljp@linux.ibm.com \
--cc=david@gibson.dropbear.id.au \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=richard.henderson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).