From: Lijun Pan <ljp@linux.ibm.com>
To: qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Cc: Lijun Pan <ljp@linux.ibm.com>,
richard.henderson@linaro.org, david@gibson.dropbear.id.au
Subject: [PATCH v4 05/11] target/ppc: add vmulld instruction
Date: Wed, 1 Jul 2020 18:43:40 -0500 [thread overview]
Message-ID: <20200701234344.91843-6-ljp@linux.ibm.com> (raw)
In-Reply-To: <20200701234344.91843-1-ljp@linux.ibm.com>
vmulld: Vector Multiply Low Doubleword.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/translate/vmx-impl.inc.c | 1 +
target/ppc/translate/vmx-ops.inc.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 6e79ffa650..8c89738552 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -807,6 +807,7 @@ GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
GEN_VXFORM(vmulosb, 4, 4);
GEN_VXFORM(vmulosh, 4, 5);
GEN_VXFORM(vmulosw, 4, 6);
+GEN_VXFORM_V(vmulld, MO_64, tcg_gen_gvec_mul, 4, 7);
GEN_VXFORM(vmuleub, 4, 8);
GEN_VXFORM(vmuleuh, 4, 9);
GEN_VXFORM(vmuleuw, 4, 10);
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index 84e05fb827..b49787ac97 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -48,6 +48,9 @@ GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \
PPC2_ISA300)
+#define GEN_VXFORM_310(name, opc2, opc3) \
+GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA310)
+
#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
@@ -104,6 +107,7 @@ GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vmulosb, 4, 4),
GEN_VXFORM(vmulosh, 4, 5),
GEN_VXFORM_207(vmulosw, 4, 6),
+GEN_VXFORM_310(vmulld, 4, 7),
GEN_VXFORM(vmuleub, 4, 8),
GEN_VXFORM(vmuleuh, 4, 9),
GEN_VXFORM_207(vmuleuw, 4, 10),
--
2.23.0
next prev parent reply other threads:[~2020-07-01 23:50 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-01 23:43 [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
2020-07-01 23:43 ` [PATCH v4 01/11] target/ppc: Introduce Power ISA 3.1 flag Lijun Pan
2020-07-05 9:07 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 02/11] target/ppc: Enable Power ISA 3.1 Lijun Pan
2020-07-05 9:08 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 03/11] target/ppc: add byte-reverse br[dwh] instructions Lijun Pan
2020-07-07 10:30 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 04/11] target/ppc: convert vmuluwm to tcg_gen_gvec_mul Lijun Pan
2020-07-08 12:22 ` David Gibson
2020-07-01 23:43 ` Lijun Pan [this message]
2020-07-13 5:11 ` [PATCH v4 05/11] target/ppc: add vmulld instruction David Gibson
2020-07-01 23:43 ` [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition Lijun Pan
2020-07-13 5:14 ` David Gibson
2020-07-13 19:20 ` Lijun Pan
2020-07-13 23:47 ` David Gibson
2020-07-14 20:28 ` Lijun Pan
2020-07-01 23:43 ` [PATCH v4 07/11] target/ppc: add vmulld to INDEX_op_mul_vec case Lijun Pan
2020-07-13 19:40 ` Lijun Pan
2020-07-01 23:43 ` [PATCH v4 08/11] target/ppc: add vmulh{su}w instructions Lijun Pan
2020-07-13 19:35 ` Lijun Pan
2020-07-01 23:43 ` [PATCH v4 09/11] fix the prototype of muls64/mulu64 Lijun Pan
2020-07-06 16:14 ` Laurent Vivier
2020-07-05 9:10 ` [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions David Gibson
2020-07-06 7:34 ` Greg Kurz
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