* [PATCH v4 01/11] target/ppc: Introduce Power ISA 3.1 flag
2020-07-01 23:43 [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
@ 2020-07-01 23:43 ` Lijun Pan
2020-07-05 9:07 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 02/11] target/ppc: Enable Power ISA 3.1 Lijun Pan
` (8 subsequent siblings)
9 siblings, 1 reply; 24+ messages in thread
From: Lijun Pan @ 2020-07-01 23:43 UTC (permalink / raw)
To: qemu-ppc, qemu-devel; +Cc: Lijun Pan, richard.henderson, david
This flag will be used for Power10 instructions.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v4: split to 01/11 and 02/11
v2: add Power ISA 3.1 flag
target/ppc/cpu.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 1988b436cb..a5e9c08dcc 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2191,6 +2191,8 @@ enum {
PPC2_PM_ISA206 = 0x0000000000040000ULL,
/* POWER ISA 3.0 */
PPC2_ISA300 = 0x0000000000080000ULL,
+ /* POWER ISA 3.1 */
+ PPC2_ISA310 = 0x0000000000100000ULL,
#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
--
2.23.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v4 01/11] target/ppc: Introduce Power ISA 3.1 flag
2020-07-01 23:43 ` [PATCH v4 01/11] target/ppc: Introduce Power ISA 3.1 flag Lijun Pan
@ 2020-07-05 9:07 ` David Gibson
0 siblings, 0 replies; 24+ messages in thread
From: David Gibson @ 2020-07-05 9:07 UTC (permalink / raw)
To: Lijun Pan; +Cc: richard.henderson, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1194 bytes --]
On Wed, Jul 01, 2020 at 06:43:36PM -0500, Lijun Pan wrote:
> This flag will be used for Power10 instructions.
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
Applied to ppc-for-5.2.
> ---
> v4: split to 01/11 and 02/11
> v2: add Power ISA 3.1 flag
>
> target/ppc/cpu.h | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index 1988b436cb..a5e9c08dcc 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2191,6 +2191,8 @@ enum {
> PPC2_PM_ISA206 = 0x0000000000040000ULL,
> /* POWER ISA 3.0 */
> PPC2_ISA300 = 0x0000000000080000ULL,
> + /* POWER ISA 3.1 */
> + PPC2_ISA310 = 0x0000000000100000ULL,
>
> #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
> PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v4 02/11] target/ppc: Enable Power ISA 3.1
2020-07-01 23:43 [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
2020-07-01 23:43 ` [PATCH v4 01/11] target/ppc: Introduce Power ISA 3.1 flag Lijun Pan
@ 2020-07-01 23:43 ` Lijun Pan
2020-07-05 9:08 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 03/11] target/ppc: add byte-reverse br[dwh] instructions Lijun Pan
` (7 subsequent siblings)
9 siblings, 1 reply; 24+ messages in thread
From: Lijun Pan @ 2020-07-01 23:43 UTC (permalink / raw)
To: qemu-ppc, qemu-devel; +Cc: Lijun Pan, richard.henderson, david
This patch enables the Power ISA 3.1 in QEMU.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v4: split to 01/11 and 02/11
v2: add Power ISA 3.1 flag
target/ppc/cpu.h | 2 +-
target/ppc/translate_init.inc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index a5e9c08dcc..ebb5a0811a 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -2201,7 +2201,7 @@ enum {
PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
- PPC2_ISA300)
+ PPC2_ISA300 | PPC2_ISA310)
};
/*****************************************************************************/
diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
index 38cb773ab4..3f72310e60 100644
--- a/target/ppc/translate_init.inc.c
+++ b/target/ppc/translate_init.inc.c
@@ -9206,7 +9206,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
- PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
+ PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_HV) |
(1ull << MSR_TM) |
--
2.23.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v4 02/11] target/ppc: Enable Power ISA 3.1
2020-07-01 23:43 ` [PATCH v4 02/11] target/ppc: Enable Power ISA 3.1 Lijun Pan
@ 2020-07-05 9:08 ` David Gibson
0 siblings, 0 replies; 24+ messages in thread
From: David Gibson @ 2020-07-05 9:08 UTC (permalink / raw)
To: Lijun Pan; +Cc: richard.henderson, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1950 bytes --]
On Wed, Jul 01, 2020 at 06:43:37PM -0500, Lijun Pan wrote:
> This patch enables the Power ISA 3.1 in QEMU.
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
Applied to ppc-for-5.2.
> ---
> v4: split to 01/11 and 02/11
> v2: add Power ISA 3.1 flag
>
> target/ppc/cpu.h | 2 +-
> target/ppc/translate_init.inc.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
> index a5e9c08dcc..ebb5a0811a 100644
> --- a/target/ppc/cpu.h
> +++ b/target/ppc/cpu.h
> @@ -2201,7 +2201,7 @@ enum {
> PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
> PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
> PPC2_FP_CVT_S64 | PPC2_TM | PPC2_PM_ISA206 | \
> - PPC2_ISA300)
> + PPC2_ISA300 | PPC2_ISA310)
> };
>
> /*****************************************************************************/
> diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.inc.c
> index 38cb773ab4..3f72310e60 100644
> --- a/target/ppc/translate_init.inc.c
> +++ b/target/ppc/translate_init.inc.c
> @@ -9206,7 +9206,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
> PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
> PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
> PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
> - PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
> + PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL | PPC2_ISA310;
> pcc->msr_mask = (1ull << MSR_SF) |
> (1ull << MSR_HV) |
> (1ull << MSR_TM) |
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v4 03/11] target/ppc: add byte-reverse br[dwh] instructions
2020-07-01 23:43 [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
2020-07-01 23:43 ` [PATCH v4 01/11] target/ppc: Introduce Power ISA 3.1 flag Lijun Pan
2020-07-01 23:43 ` [PATCH v4 02/11] target/ppc: Enable Power ISA 3.1 Lijun Pan
@ 2020-07-01 23:43 ` Lijun Pan
2020-07-07 10:30 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 04/11] target/ppc: convert vmuluwm to tcg_gen_gvec_mul Lijun Pan
` (6 subsequent siblings)
9 siblings, 1 reply; 24+ messages in thread
From: Lijun Pan @ 2020-07-01 23:43 UTC (permalink / raw)
To: qemu-ppc, qemu-devel; +Cc: Lijun Pan, richard.henderson, david
POWER ISA 3.1 introduces following byte-reverse instructions:
brd: Byte-Reverse Doubleword X-form
brw: Byte-Reverse Word X-form
brh: Byte-Reverse Halfword X-form
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v4: make it compile on all targets
v3: fix the store issue in br[dwh]
simplify brw implementation
add "if defined(TARGET_PPC64)"
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4ce3d664b5..590c3e3bc7 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6971,7 +6971,47 @@ static void gen_dform3D(DisasContext *ctx)
return gen_invalid(ctx);
}
+#if defined(TARGET_PPC64)
+/* brd */
+static void gen_brd(DisasContext *ctx)
+{
+ tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+}
+
+/* brw */
+static void gen_brw(DisasContext *ctx)
+{
+ tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
+ tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32);
+
+}
+
+/* brh */
+static void gen_brh(DisasContext *ctx)
+{
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull);
+ tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
+ tcg_gen_and_i64(t2, t1, t0);
+ tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0);
+ tcg_gen_shli_i64(t1, t1, 8);
+ tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
+
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+}
+#endif
+
static opcode_t opcodes[] = {
+#if defined(TARGET_PPC64)
+GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
+GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
+GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
+#endif
GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
--
2.23.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v4 03/11] target/ppc: add byte-reverse br[dwh] instructions
2020-07-01 23:43 ` [PATCH v4 03/11] target/ppc: add byte-reverse br[dwh] instructions Lijun Pan
@ 2020-07-07 10:30 ` David Gibson
0 siblings, 0 replies; 24+ messages in thread
From: David Gibson @ 2020-07-07 10:30 UTC (permalink / raw)
To: Lijun Pan; +Cc: richard.henderson, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2667 bytes --]
On Wed, Jul 01, 2020 at 06:43:38PM -0500, Lijun Pan wrote:
> POWER ISA 3.1 introduces following byte-reverse instructions:
> brd: Byte-Reverse Doubleword X-form
> brw: Byte-Reverse Word X-form
> brh: Byte-Reverse Halfword X-form
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
Applied to ppc-for-5.2.
> ---
> v4: make it compile on all targets
> v3: fix the store issue in br[dwh]
> simplify brw implementation
> add "if defined(TARGET_PPC64)"
> v2: fix coding style
> use Power ISA 3.1 flag
>
> target/ppc/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 4ce3d664b5..590c3e3bc7 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -6971,7 +6971,47 @@ static void gen_dform3D(DisasContext *ctx)
> return gen_invalid(ctx);
> }
>
> +#if defined(TARGET_PPC64)
> +/* brd */
> +static void gen_brd(DisasContext *ctx)
> +{
> + tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
> +}
> +
> +/* brw */
> +static void gen_brw(DisasContext *ctx)
> +{
> + tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32);
> +
> +}
> +
> +/* brh */
> +static void gen_brh(DisasContext *ctx)
> +{
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + TCGv_i64 t1 = tcg_temp_new_i64();
> + TCGv_i64 t2 = tcg_temp_new_i64();
> +
> + tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull);
> + tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
> + tcg_gen_and_i64(t2, t1, t0);
> + tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0);
> + tcg_gen_shli_i64(t1, t1, 8);
> + tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
> +
> + tcg_temp_free_i64(t0);
> + tcg_temp_free_i64(t1);
> + tcg_temp_free_i64(t2);
> +}
> +#endif
> +
> static opcode_t opcodes[] = {
> +#if defined(TARGET_PPC64)
> +GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
> +GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
> +GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
> +#endif
> GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
> GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
> GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v4 04/11] target/ppc: convert vmuluwm to tcg_gen_gvec_mul
2020-07-01 23:43 [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
` (2 preceding siblings ...)
2020-07-01 23:43 ` [PATCH v4 03/11] target/ppc: add byte-reverse br[dwh] instructions Lijun Pan
@ 2020-07-01 23:43 ` Lijun Pan
2020-07-08 12:22 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 05/11] target/ppc: add vmulld instruction Lijun Pan
` (5 subsequent siblings)
9 siblings, 1 reply; 24+ messages in thread
From: Lijun Pan @ 2020-07-01 23:43 UTC (permalink / raw)
To: qemu-ppc, qemu-devel; +Cc: Lijun Pan, richard.henderson, david
Convert the original implementation of vmuluwm to the more generic
tcg_gen_gvec_mul.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
v3: newly introduced
target/ppc/helper.h | 1 -
target/ppc/int_helper.c | 13 -------------
target/ppc/translate/vmx-impl.inc.c | 2 +-
3 files changed, 1 insertion(+), 15 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 2dfa1c6942..69416b6d7c 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -184,7 +184,6 @@ DEF_HELPER_3(vmulosw, void, avr, avr, avr)
DEF_HELPER_3(vmuloub, void, avr, avr, avr)
DEF_HELPER_3(vmulouh, void, avr, avr, avr)
DEF_HELPER_3(vmulouw, void, avr, avr, avr)
-DEF_HELPER_3(vmuluwm, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_3(vsrv, void, avr, avr, avr)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index be53cd6f68..bd3e6d7cc7 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -523,19 +523,6 @@ void helper_vprtybq(ppc_avr_t *r, ppc_avr_t *b)
r->VsrD(0) = 0;
}
-#define VARITH_DO(name, op, element) \
- void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
- { \
- int i; \
- \
- for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
- r->element[i] = a->element[i] op b->element[i]; \
- } \
- }
-VARITH_DO(muluwm, *, u32)
-#undef VARITH_DO
-#undef VARITH
-
#define VARITHFP(suffix, func) \
void helper_v##suffix(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, \
ppc_avr_t *b) \
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 403ed3a01c..6e79ffa650 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -801,7 +801,7 @@ static void trans_vclzd(DisasContext *ctx)
GEN_VXFORM(vmuloub, 4, 0);
GEN_VXFORM(vmulouh, 4, 1);
GEN_VXFORM(vmulouw, 4, 2);
-GEN_VXFORM(vmuluwm, 4, 2);
+GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
GEN_VXFORM(vmulosb, 4, 4);
--
2.23.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v4 04/11] target/ppc: convert vmuluwm to tcg_gen_gvec_mul
2020-07-01 23:43 ` [PATCH v4 04/11] target/ppc: convert vmuluwm to tcg_gen_gvec_mul Lijun Pan
@ 2020-07-08 12:22 ` David Gibson
0 siblings, 0 replies; 24+ messages in thread
From: David Gibson @ 2020-07-08 12:22 UTC (permalink / raw)
To: Lijun Pan; +Cc: richard.henderson, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 3107 bytes --]
On Wed, Jul 01, 2020 at 06:43:39PM -0500, Lijun Pan wrote:
> Convert the original implementation of vmuluwm to the more generic
> tcg_gen_gvec_mul.
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
Applied to ppc-for-5.2.
> ---
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> v3: newly introduced
>
> target/ppc/helper.h | 1 -
> target/ppc/int_helper.c | 13 -------------
> target/ppc/translate/vmx-impl.inc.c | 2 +-
> 3 files changed, 1 insertion(+), 15 deletions(-)
>
> diff --git a/target/ppc/helper.h b/target/ppc/helper.h
> index 2dfa1c6942..69416b6d7c 100644
> --- a/target/ppc/helper.h
> +++ b/target/ppc/helper.h
> @@ -184,7 +184,6 @@ DEF_HELPER_3(vmulosw, void, avr, avr, avr)
> DEF_HELPER_3(vmuloub, void, avr, avr, avr)
> DEF_HELPER_3(vmulouh, void, avr, avr, avr)
> DEF_HELPER_3(vmulouw, void, avr, avr, avr)
> -DEF_HELPER_3(vmuluwm, void, avr, avr, avr)
> DEF_HELPER_3(vslo, void, avr, avr, avr)
> DEF_HELPER_3(vsro, void, avr, avr, avr)
> DEF_HELPER_3(vsrv, void, avr, avr, avr)
> diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
> index be53cd6f68..bd3e6d7cc7 100644
> --- a/target/ppc/int_helper.c
> +++ b/target/ppc/int_helper.c
> @@ -523,19 +523,6 @@ void helper_vprtybq(ppc_avr_t *r, ppc_avr_t *b)
> r->VsrD(0) = 0;
> }
>
> -#define VARITH_DO(name, op, element) \
> - void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> - { \
> - int i; \
> - \
> - for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> - r->element[i] = a->element[i] op b->element[i]; \
> - } \
> - }
> -VARITH_DO(muluwm, *, u32)
> -#undef VARITH_DO
> -#undef VARITH
> -
> #define VARITHFP(suffix, func) \
> void helper_v##suffix(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, \
> ppc_avr_t *b) \
> diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
> index 403ed3a01c..6e79ffa650 100644
> --- a/target/ppc/translate/vmx-impl.inc.c
> +++ b/target/ppc/translate/vmx-impl.inc.c
> @@ -801,7 +801,7 @@ static void trans_vclzd(DisasContext *ctx)
> GEN_VXFORM(vmuloub, 4, 0);
> GEN_VXFORM(vmulouh, 4, 1);
> GEN_VXFORM(vmulouw, 4, 2);
> -GEN_VXFORM(vmuluwm, 4, 2);
> +GEN_VXFORM_V(vmuluwm, MO_32, tcg_gen_gvec_mul, 4, 2);
> GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
> vmuluwm, PPC_NONE, PPC2_ALTIVEC_207)
> GEN_VXFORM(vmulosb, 4, 4);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v4 05/11] target/ppc: add vmulld instruction
2020-07-01 23:43 [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
` (3 preceding siblings ...)
2020-07-01 23:43 ` [PATCH v4 04/11] target/ppc: convert vmuluwm to tcg_gen_gvec_mul Lijun Pan
@ 2020-07-01 23:43 ` Lijun Pan
2020-07-13 5:11 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition Lijun Pan
` (4 subsequent siblings)
9 siblings, 1 reply; 24+ messages in thread
From: Lijun Pan @ 2020-07-01 23:43 UTC (permalink / raw)
To: qemu-ppc, qemu-devel; +Cc: Lijun Pan, richard.henderson, david
vmulld: Vector Multiply Low Doubleword.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/translate/vmx-impl.inc.c | 1 +
target/ppc/translate/vmx-ops.inc.c | 4 ++++
2 files changed, 5 insertions(+)
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 6e79ffa650..8c89738552 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -807,6 +807,7 @@ GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
GEN_VXFORM(vmulosb, 4, 4);
GEN_VXFORM(vmulosh, 4, 5);
GEN_VXFORM(vmulosw, 4, 6);
+GEN_VXFORM_V(vmulld, MO_64, tcg_gen_gvec_mul, 4, 7);
GEN_VXFORM(vmuleub, 4, 8);
GEN_VXFORM(vmuleuh, 4, 9);
GEN_VXFORM(vmuleuw, 4, 10);
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index 84e05fb827..b49787ac97 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -48,6 +48,9 @@ GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \
PPC2_ISA300)
+#define GEN_VXFORM_310(name, opc2, opc3) \
+GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA310)
+
#define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
@@ -104,6 +107,7 @@ GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vmulosb, 4, 4),
GEN_VXFORM(vmulosh, 4, 5),
GEN_VXFORM_207(vmulosw, 4, 6),
+GEN_VXFORM_310(vmulld, 4, 7),
GEN_VXFORM(vmuleub, 4, 8),
GEN_VXFORM(vmuleuh, 4, 9),
GEN_VXFORM_207(vmuleuw, 4, 10),
--
2.23.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v4 05/11] target/ppc: add vmulld instruction
2020-07-01 23:43 ` [PATCH v4 05/11] target/ppc: add vmulld instruction Lijun Pan
@ 2020-07-13 5:11 ` David Gibson
0 siblings, 0 replies; 24+ messages in thread
From: David Gibson @ 2020-07-13 5:11 UTC (permalink / raw)
To: Lijun Pan; +Cc: richard.henderson, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 2291 bytes --]
On Wed, Jul 01, 2020 at 06:43:40PM -0500, Lijun Pan wrote:
> vmulld: Vector Multiply Low Doubleword.
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
Applied to ppc-for-5.2.
> ---
> v4: add missing changes, and split to 5/11, 6/11, 7/11
> v3: use tcg_gen_gvec_mul()
> v2: fix coding style
> use Power ISA 3.1 flag
>
> target/ppc/translate/vmx-impl.inc.c | 1 +
> target/ppc/translate/vmx-ops.inc.c | 4 ++++
> 2 files changed, 5 insertions(+)
>
> diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
> index 6e79ffa650..8c89738552 100644
> --- a/target/ppc/translate/vmx-impl.inc.c
> +++ b/target/ppc/translate/vmx-impl.inc.c
> @@ -807,6 +807,7 @@ GEN_VXFORM_DUAL(vmulouw, PPC_ALTIVEC, PPC_NONE,
> GEN_VXFORM(vmulosb, 4, 4);
> GEN_VXFORM(vmulosh, 4, 5);
> GEN_VXFORM(vmulosw, 4, 6);
> +GEN_VXFORM_V(vmulld, MO_64, tcg_gen_gvec_mul, 4, 7);
> GEN_VXFORM(vmuleub, 4, 8);
> GEN_VXFORM(vmuleuh, 4, 9);
> GEN_VXFORM(vmuleuw, 4, 10);
> diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
> index 84e05fb827..b49787ac97 100644
> --- a/target/ppc/translate/vmx-ops.inc.c
> +++ b/target/ppc/translate/vmx-ops.inc.c
> @@ -48,6 +48,9 @@ GEN_HANDLER_E(name, 0x04, opc2, opc3, inval, PPC_NONE, PPC2_ISA300)
> GEN_HANDLER_E_2(name, 0x04, opc2, opc3, opc4, 0x00000000, PPC_NONE, \
> PPC2_ISA300)
>
> +#define GEN_VXFORM_310(name, opc2, opc3) \
> +GEN_HANDLER_E(name, 0x04, opc2, opc3, 0x00000000, PPC_NONE, PPC2_ISA310)
> +
> #define GEN_VXFORM_DUAL(name0, name1, opc2, opc3, type0, type1) \
> GEN_HANDLER_E(name0##_##name1, 0x4, opc2, opc3, 0x00000000, type0, type1)
>
> @@ -104,6 +107,7 @@ GEN_VXFORM_DUAL(vmulouw, vmuluwm, 4, 2, PPC_ALTIVEC, PPC_NONE),
> GEN_VXFORM(vmulosb, 4, 4),
> GEN_VXFORM(vmulosh, 4, 5),
> GEN_VXFORM_207(vmulosw, 4, 6),
> +GEN_VXFORM_310(vmulld, 4, 7),
> GEN_VXFORM(vmuleub, 4, 8),
> GEN_VXFORM(vmuleuh, 4, 9),
> GEN_VXFORM_207(vmuleuw, 4, 10),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition
2020-07-01 23:43 [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
` (4 preceding siblings ...)
2020-07-01 23:43 ` [PATCH v4 05/11] target/ppc: add vmulld instruction Lijun Pan
@ 2020-07-01 23:43 ` Lijun Pan
2020-07-13 5:14 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 07/11] target/ppc: add vmulld to INDEX_op_mul_vec case Lijun Pan
` (3 subsequent siblings)
9 siblings, 1 reply; 24+ messages in thread
From: Lijun Pan @ 2020-07-01 23:43 UTC (permalink / raw)
To: qemu-ppc, qemu-devel; +Cc: Lijun Pan, richard.henderson, david
Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
use Power ISA 3.1 flag
include/elf.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/elf.h b/include/elf.h
index 8fbfe60e09..1858b95acf 100644
--- a/include/elf.h
+++ b/include/elf.h
@@ -554,6 +554,7 @@ typedef struct {
#define PPC_FEATURE2_HTM_NOSC 0x01000000
#define PPC_FEATURE2_ARCH_3_00 0x00800000
#define PPC_FEATURE2_HAS_IEEE128 0x00400000
+#define PPC_FEATURE2_ARCH_3_10 0x00200000
/* Bits present in AT_HWCAP for Sparc. */
--
2.23.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition
2020-07-01 23:43 ` [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition Lijun Pan
@ 2020-07-13 5:14 ` David Gibson
2020-07-13 19:20 ` Lijun Pan
0 siblings, 1 reply; 24+ messages in thread
From: David Gibson @ 2020-07-13 5:14 UTC (permalink / raw)
To: Lijun Pan; +Cc: richard.henderson, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1187 bytes --]
On Wed, Jul 01, 2020 at 06:43:41PM -0500, Lijun Pan wrote:
> Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions.
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
> ---
> v4: add missing changes, and split to 5/11, 6/11, 7/11
> v3: use tcg_gen_gvec_mul()
> v2: fix coding style
> use Power ISA 3.1 flag
>
> include/elf.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/include/elf.h b/include/elf.h
> index 8fbfe60e09..1858b95acf 100644
> --- a/include/elf.h
> +++ b/include/elf.h
> @@ -554,6 +554,7 @@ typedef struct {
> #define PPC_FEATURE2_HTM_NOSC 0x01000000
> #define PPC_FEATURE2_ARCH_3_00 0x00800000
> #define PPC_FEATURE2_HAS_IEEE128 0x00400000
> +#define PPC_FEATURE2_ARCH_3_10 0x00200000
>
> /* Bits present in AT_HWCAP for Sparc. */
Um.. in the corresponding #defines in the kernel 0x00200000 is given
to PPC_FEATURE2_DARN, and several more bits are allocated past that
point.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition
2020-07-13 5:14 ` David Gibson
@ 2020-07-13 19:20 ` Lijun Pan
2020-07-13 23:47 ` David Gibson
0 siblings, 1 reply; 24+ messages in thread
From: Lijun Pan @ 2020-07-13 19:20 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, Richard Henderson, Lijun Pan, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1171 bytes --]
> On Jul 13, 2020, at 12:14 AM, David Gibson <david@gibson.dropbear.id.au> wrote:
>
> On Wed, Jul 01, 2020 at 06:43:41PM -0500, Lijun Pan wrote:
>> Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions.
>>
>> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
>> ---
>> v4: add missing changes, and split to 5/11, 6/11, 7/11
>> v3: use tcg_gen_gvec_mul()
>> v2: fix coding style
>> use Power ISA 3.1 flag
>>
>> include/elf.h | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/include/elf.h b/include/elf.h
>> index 8fbfe60e09..1858b95acf 100644
>> --- a/include/elf.h
>> +++ b/include/elf.h
>> @@ -554,6 +554,7 @@ typedef struct {
>> #define PPC_FEATURE2_HTM_NOSC 0x01000000
>> #define PPC_FEATURE2_ARCH_3_00 0x00800000
>> #define PPC_FEATURE2_HAS_IEEE128 0x00400000
>> +#define PPC_FEATURE2_ARCH_3_10 0x00200000
>>
>> /* Bits present in AT_HWCAP for Sparc. */
>
>
> Um.. in the corresponding #defines in the kernel 0x00200000 is given
> to PPC_FEATURE2_DARN, and several more bits are allocated past that
> point.
>
Then what do you recommend to use?
Thanks,
Lijun
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^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition
2020-07-13 19:20 ` Lijun Pan
@ 2020-07-13 23:47 ` David Gibson
2020-07-14 20:28 ` Lijun Pan
0 siblings, 1 reply; 24+ messages in thread
From: David Gibson @ 2020-07-13 23:47 UTC (permalink / raw)
To: Lijun Pan; +Cc: qemu-ppc, Richard Henderson, Lijun Pan, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1626 bytes --]
On Mon, Jul 13, 2020 at 02:20:20PM -0500, Lijun Pan wrote:
>
>
> > On Jul 13, 2020, at 12:14 AM, David Gibson <david@gibson.dropbear.id.au> wrote:
> >
> > On Wed, Jul 01, 2020 at 06:43:41PM -0500, Lijun Pan wrote:
> >> Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions.
> >>
> >> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
> >> ---
> >> v4: add missing changes, and split to 5/11, 6/11, 7/11
> >> v3: use tcg_gen_gvec_mul()
> >> v2: fix coding style
> >> use Power ISA 3.1 flag
> >>
> >> include/elf.h | 1 +
> >> 1 file changed, 1 insertion(+)
> >>
> >> diff --git a/include/elf.h b/include/elf.h
> >> index 8fbfe60e09..1858b95acf 100644
> >> --- a/include/elf.h
> >> +++ b/include/elf.h
> >> @@ -554,6 +554,7 @@ typedef struct {
> >> #define PPC_FEATURE2_HTM_NOSC 0x01000000
> >> #define PPC_FEATURE2_ARCH_3_00 0x00800000
> >> #define PPC_FEATURE2_HAS_IEEE128 0x00400000
> >> +#define PPC_FEATURE2_ARCH_3_10 0x00200000
> >>
> >> /* Bits present in AT_HWCAP for Sparc. */
> >
> >
> > Um.. in the corresponding #defines in the kernel 0x00200000 is given
> > to PPC_FEATURE2_DARN, and several more bits are allocated past that
> > point.
>
> Then what do you recommend to use?
This is part of exposed userland ABI, so it needs to be standardized
at least semi-formally. I'm not actually sure who allocates these in
general.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition
2020-07-13 23:47 ` David Gibson
@ 2020-07-14 20:28 ` Lijun Pan
0 siblings, 0 replies; 24+ messages in thread
From: Lijun Pan @ 2020-07-14 20:28 UTC (permalink / raw)
To: David Gibson, anton; +Cc: Richard Henderson, qemu-ppc, qemu-devel, Lijun Pan
[-- Attachment #1: Type: text/plain, Size: 1909 bytes --]
> On Jul 13, 2020, at 6:47 PM, David Gibson <david@gibson.dropbear.id.au> wrote:
>
> On Mon, Jul 13, 2020 at 02:20:20PM -0500, Lijun Pan wrote:
>>
>>
>>> On Jul 13, 2020, at 12:14 AM, David Gibson <david@gibson.dropbear.id.au> wrote:
>>>
>>> On Wed, Jul 01, 2020 at 06:43:41PM -0500, Lijun Pan wrote:
>>>> Add PPC2_FEATURE2_ARCH_3_10 to the PowerPC AT_HWCAP2 definitions.
>>>>
>>>> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
>>>> ---
>>>> v4: add missing changes, and split to 5/11, 6/11, 7/11
>>>> v3: use tcg_gen_gvec_mul()
>>>> v2: fix coding style
>>>> use Power ISA 3.1 flag
>>>>
>>>> include/elf.h | 1 +
>>>> 1 file changed, 1 insertion(+)
>>>>
>>>> diff --git a/include/elf.h b/include/elf.h
>>>> index 8fbfe60e09..1858b95acf 100644
>>>> --- a/include/elf.h
>>>> +++ b/include/elf.h
>>>> @@ -554,6 +554,7 @@ typedef struct {
>>>> #define PPC_FEATURE2_HTM_NOSC 0x01000000
>>>> #define PPC_FEATURE2_ARCH_3_00 0x00800000
>>>> #define PPC_FEATURE2_HAS_IEEE128 0x00400000
>>>> +#define PPC_FEATURE2_ARCH_3_10 0x00200000
>>>>
>>>> /* Bits present in AT_HWCAP for Sparc. */
>>>
>>>
>>> Um.. in the corresponding #defines in the kernel 0x00200000 is given
>>> to PPC_FEATURE2_DARN, and several more bits are allocated past that
>>> point.
>>
>> Then what do you recommend to use?
>
> This is part of exposed userland ABI, so it needs to be standardized
> at least semi-formally. I'm not actually sure who allocates these in
> general.
Anton,
Do you know the allocation standard since you made the last change into elf.h?
Lijun
>
> --
> David Gibson | I'll have my music baroque, and my code
> david AT gibson.dropbear.id.au <http://gibson.dropbear.id.au/> | minimalist, thank you. NOT _the_ _other_
> | _way_ _around_!
> http://www.ozlabs.org/~dgibson <http://www.ozlabs.org/~dgibson>
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^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v4 07/11] target/ppc: add vmulld to INDEX_op_mul_vec case
2020-07-01 23:43 [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
` (5 preceding siblings ...)
2020-07-01 23:43 ` [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition Lijun Pan
@ 2020-07-01 23:43 ` Lijun Pan
2020-07-13 19:40 ` Lijun Pan
2020-07-01 23:43 ` [PATCH v4 08/11] target/ppc: add vmulh{su}w instructions Lijun Pan
` (2 subsequent siblings)
9 siblings, 1 reply; 24+ messages in thread
From: Lijun Pan @ 2020-07-01 23:43 UTC (permalink / raw)
To: qemu-ppc, qemu-devel; +Cc: Lijun Pan, richard.henderson, david
Group vmuluwm and vmulld. Make vmulld-specific
changes since it belongs to new ISA 3.1.
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
v4: add missing changes, and split to 5/11, 6/11, 7/11
v3: use tcg_gen_gvec_mul()
v2: fix coding style
use Power ISA 3.1 flag
tcg/ppc/tcg-target.h | 2 ++
tcg/ppc/tcg-target.inc.c | 12 ++++++++++--
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
index 4fa21f0e71..ff1249ef8e 100644
--- a/tcg/ppc/tcg-target.h
+++ b/tcg/ppc/tcg-target.h
@@ -63,6 +63,7 @@ typedef enum {
tcg_isa_2_06,
tcg_isa_2_07,
tcg_isa_3_00,
+ tcg_isa_3_10,
} TCGPowerISA;
extern TCGPowerISA have_isa;
@@ -72,6 +73,7 @@ extern bool have_vsx;
#define have_isa_2_06 (have_isa >= tcg_isa_2_06)
#define have_isa_2_07 (have_isa >= tcg_isa_2_07)
#define have_isa_3_00 (have_isa >= tcg_isa_3_00)
+#define have_isa_3_10 (have_isa >= tcg_isa_3_10)
/* optional instructions automatically implemented */
#define TCG_TARGET_HAS_ext8u_i32 0 /* andi */
diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
index ee1f9227c1..caa8985b46 100644
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.inc.c
@@ -564,6 +564,7 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
#define VMULOUH VX4(72)
#define VMULOUW VX4(136) /* v2.07 */
#define VMULUWM VX4(137) /* v2.07 */
+#define VMULLD VX4(457) /* v3.10 */
#define VMSUMUHM VX4(38)
#define VMRGHB VX4(12)
@@ -3015,6 +3016,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
return -1;
case MO_32:
return have_isa_2_07 ? 1 : -1;
+ case MO_64:
+ return have_isa_3_10;
}
return 0;
case INDEX_op_bitsel_vec:
@@ -3149,6 +3152,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static const uint32_t
add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
+ mul_op[4] = { 0, 0, VMULUWM, VMULLD },
neg_op[4] = { 0, 0, VNEGW, VNEGD },
eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 },
@@ -3199,8 +3203,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
a1 = 0;
break;
case INDEX_op_mul_vec:
- tcg_debug_assert(vece == MO_32 && have_isa_2_07);
- insn = VMULUWM;
+ insn = mul_op[vece];
break;
case INDEX_op_ssadd_vec:
insn = ssadd_op[vece];
@@ -3709,6 +3712,11 @@ static void tcg_target_init(TCGContext *s)
have_isa = tcg_isa_3_00;
}
#endif
+#ifdef PPC_FEATURE2_ARCH_3_10
+ if (hwcap2 & PPC_FEATURE2_ARCH_3_10) {
+ have_isa = tcg_isa_3_10;
+ }
+#endif
#ifdef PPC_FEATURE2_HAS_ISEL
/* Prefer explicit instruction from the kernel. */
--
2.23.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v4 07/11] target/ppc: add vmulld to INDEX_op_mul_vec case
2020-07-01 23:43 ` [PATCH v4 07/11] target/ppc: add vmulld to INDEX_op_mul_vec case Lijun Pan
@ 2020-07-13 19:40 ` Lijun Pan
0 siblings, 0 replies; 24+ messages in thread
From: Lijun Pan @ 2020-07-13 19:40 UTC (permalink / raw)
To: Lijun Pan; +Cc: richard.henderson, qemu-ppc, qemu-devel, david
> On Jul 1, 2020, at 6:43 PM, Lijun Pan <ljp@linux.ibm.com> wrote:
>
> Group vmuluwm and vmulld. Make vmulld-specific
> changes since it belongs to new ISA 3.1.
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
> ---
> v4: add missing changes, and split to 5/11, 6/11, 7/11
> v3: use tcg_gen_gvec_mul()
> v2: fix coding style
> use Power ISA 3.1 flag
>
Richard,
Do you have any opinion on this one?
Thanks,
Lijun
> tcg/ppc/tcg-target.h | 2 ++
> tcg/ppc/tcg-target.inc.c | 12 ++++++++++--
> 2 files changed, 12 insertions(+), 2 deletions(-)
>
> diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h
> index 4fa21f0e71..ff1249ef8e 100644
> --- a/tcg/ppc/tcg-target.h
> +++ b/tcg/ppc/tcg-target.h
> @@ -63,6 +63,7 @@ typedef enum {
> tcg_isa_2_06,
> tcg_isa_2_07,
> tcg_isa_3_00,
> + tcg_isa_3_10,
> } TCGPowerISA;
>
> extern TCGPowerISA have_isa;
> @@ -72,6 +73,7 @@ extern bool have_vsx;
> #define have_isa_2_06 (have_isa >= tcg_isa_2_06)
> #define have_isa_2_07 (have_isa >= tcg_isa_2_07)
> #define have_isa_3_00 (have_isa >= tcg_isa_3_00)
> +#define have_isa_3_10 (have_isa >= tcg_isa_3_10)
>
> /* optional instructions automatically implemented */
> #define TCG_TARGET_HAS_ext8u_i32 0 /* andi */
> diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.inc.c
> index ee1f9227c1..caa8985b46 100644
> --- a/tcg/ppc/tcg-target.inc.c
> +++ b/tcg/ppc/tcg-target.inc.c
> @@ -564,6 +564,7 @@ static int tcg_target_const_match(tcg_target_long val, TCGType type,
> #define VMULOUH VX4(72)
> #define VMULOUW VX4(136) /* v2.07 */
> #define VMULUWM VX4(137) /* v2.07 */
> +#define VMULLD VX4(457) /* v3.10 */
> #define VMSUMUHM VX4(38)
>
> #define VMRGHB VX4(12)
> @@ -3015,6 +3016,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
> return -1;
> case MO_32:
> return have_isa_2_07 ? 1 : -1;
> + case MO_64:
> + return have_isa_3_10;
> }
> return 0;
> case INDEX_op_bitsel_vec:
> @@ -3149,6 +3152,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
> static const uint32_t
> add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM },
> sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM },
> + mul_op[4] = { 0, 0, VMULUWM, VMULLD },
> neg_op[4] = { 0, 0, VNEGW, VNEGD },
> eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD },
> ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 },
> @@ -3199,8 +3203,7 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
> a1 = 0;
> break;
> case INDEX_op_mul_vec:
> - tcg_debug_assert(vece == MO_32 && have_isa_2_07);
> - insn = VMULUWM;
> + insn = mul_op[vece];
> break;
> case INDEX_op_ssadd_vec:
> insn = ssadd_op[vece];
> @@ -3709,6 +3712,11 @@ static void tcg_target_init(TCGContext *s)
> have_isa = tcg_isa_3_00;
> }
> #endif
> +#ifdef PPC_FEATURE2_ARCH_3_10
> + if (hwcap2 & PPC_FEATURE2_ARCH_3_10) {
> + have_isa = tcg_isa_3_10;
> + }
> +#endif
>
> #ifdef PPC_FEATURE2_HAS_ISEL
> /* Prefer explicit instruction from the kernel. */
> --
> 2.23.0
>
>
^ permalink raw reply [flat|nested] 24+ messages in thread
* [PATCH v4 08/11] target/ppc: add vmulh{su}w instructions
2020-07-01 23:43 [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
` (6 preceding siblings ...)
2020-07-01 23:43 ` [PATCH v4 07/11] target/ppc: add vmulld to INDEX_op_mul_vec case Lijun Pan
@ 2020-07-01 23:43 ` Lijun Pan
2020-07-13 19:35 ` Lijun Pan
2020-07-01 23:43 ` [PATCH v4 09/11] fix the prototype of muls64/mulu64 Lijun Pan
2020-07-05 9:10 ` [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions David Gibson
9 siblings, 1 reply; 24+ messages in thread
From: Lijun Pan @ 2020-07-01 23:43 UTC (permalink / raw)
To: qemu-ppc, qemu-devel; +Cc: Lijun Pan, richard.henderson, david
vmulhsw: Vector Multiply High Signed Word
vmulhuw: Vector Multiply High Unsigned Word
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
v3: inline the helper_vmulh{su}w multiply directly instead of using macro
v2: fix coding style
use Power ISA 3.1 flag
target/ppc/helper.h | 2 ++
target/ppc/int_helper.c | 19 +++++++++++++++++++
target/ppc/translate/vmx-impl.inc.c | 6 ++++++
target/ppc/translate/vmx-ops.inc.c | 4 ++--
4 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/target/ppc/helper.h b/target/ppc/helper.h
index 69416b6d7c..3b3013866a 100644
--- a/target/ppc/helper.h
+++ b/target/ppc/helper.h
@@ -184,6 +184,8 @@ DEF_HELPER_3(vmulosw, void, avr, avr, avr)
DEF_HELPER_3(vmuloub, void, avr, avr, avr)
DEF_HELPER_3(vmulouh, void, avr, avr, avr)
DEF_HELPER_3(vmulouw, void, avr, avr, avr)
+DEF_HELPER_3(vmulhsw, void, avr, avr, avr)
+DEF_HELPER_3(vmulhuw, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
DEF_HELPER_3(vsrv, void, avr, avr, avr)
diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index bd3e6d7cc7..a3a20821fc 100644
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -1086,6 +1086,25 @@ VMUL(uw, u32, VsrW, VsrD, uint64_t)
#undef VMUL_DO_ODD
#undef VMUL
+void helper_vmulhsw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ r->s32[i] = (int32_t)(((int64_t)a->s32[i] * (int64_t)b->s32[i]) >> 32);
+ }
+}
+
+void helper_vmulhuw(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+
+ for (i = 0; i < 4; i++) {
+ r->u32[i] = (uint32_t)(((uint64_t)a->u32[i] *
+ (uint64_t)b->u32[i]) >> 32);
+ }
+}
+
void helper_vperm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
ppc_avr_t *c)
{
diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.inc.c
index 8c89738552..50bac375fc 100644
--- a/target/ppc/translate/vmx-impl.inc.c
+++ b/target/ppc/translate/vmx-impl.inc.c
@@ -811,9 +811,15 @@ GEN_VXFORM_V(vmulld, MO_64, tcg_gen_gvec_mul, 4, 7);
GEN_VXFORM(vmuleub, 4, 8);
GEN_VXFORM(vmuleuh, 4, 9);
GEN_VXFORM(vmuleuw, 4, 10);
+GEN_VXFORM(vmulhuw, 4, 10);
+GEN_VXFORM_DUAL(vmuleuw, PPC_ALTIVEC, PPC_NONE,
+ vmulhuw, PPC_NONE, PPC2_ISA310);
GEN_VXFORM(vmulesb, 4, 12);
GEN_VXFORM(vmulesh, 4, 13);
GEN_VXFORM(vmulesw, 4, 14);
+GEN_VXFORM(vmulhsw, 4, 14);
+GEN_VXFORM_DUAL(vmulesw, PPC_ALTIVEC, PPC_NONE,
+ vmulhsw, PPC_NONE, PPC2_ISA310);
GEN_VXFORM_V(vslb, MO_8, tcg_gen_gvec_shlv, 2, 4);
GEN_VXFORM_V(vslh, MO_16, tcg_gen_gvec_shlv, 2, 5);
GEN_VXFORM_V(vslw, MO_32, tcg_gen_gvec_shlv, 2, 6);
diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.inc.c
index b49787ac97..29701ad778 100644
--- a/target/ppc/translate/vmx-ops.inc.c
+++ b/target/ppc/translate/vmx-ops.inc.c
@@ -110,10 +110,10 @@ GEN_VXFORM_207(vmulosw, 4, 6),
GEN_VXFORM_310(vmulld, 4, 7),
GEN_VXFORM(vmuleub, 4, 8),
GEN_VXFORM(vmuleuh, 4, 9),
-GEN_VXFORM_207(vmuleuw, 4, 10),
+GEN_VXFORM_DUAL(vmuleuw, vmulhuw, 4, 10, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vmulesb, 4, 12),
GEN_VXFORM(vmulesh, 4, 13),
-GEN_VXFORM_207(vmulesw, 4, 14),
+GEN_VXFORM_DUAL(vmulesw, vmulhsw, 4, 14, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vslb, 2, 4),
GEN_VXFORM(vslh, 2, 5),
GEN_VXFORM_DUAL(vslw, vrlwnm, 2, 6, PPC_ALTIVEC, PPC_NONE),
--
2.23.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* [PATCH v4 09/11] fix the prototype of muls64/mulu64
2020-07-01 23:43 [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
` (7 preceding siblings ...)
2020-07-01 23:43 ` [PATCH v4 08/11] target/ppc: add vmulh{su}w instructions Lijun Pan
@ 2020-07-01 23:43 ` Lijun Pan
2020-07-06 16:14 ` Laurent Vivier
2020-07-05 9:10 ` [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions David Gibson
9 siblings, 1 reply; 24+ messages in thread
From: Lijun Pan @ 2020-07-01 23:43 UTC (permalink / raw)
To: qemu-ppc, qemu-devel; +Cc: Lijun Pan, richard.henderson, david
The prototypes of muls64/mulu64 in host-utils.h should match the
definitions in host-utils.c
Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
---
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
no change since v1
include/qemu/host-utils.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
index 4cd170e6cd..cdca2991d8 100644
--- a/include/qemu/host-utils.h
+++ b/include/qemu/host-utils.h
@@ -77,8 +77,8 @@ static inline int divs128(int64_t *plow, int64_t *phigh, int64_t divisor)
}
}
#else
-void muls64(uint64_t *phigh, uint64_t *plow, int64_t a, int64_t b);
-void mulu64(uint64_t *phigh, uint64_t *plow, uint64_t a, uint64_t b);
+void muls64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b);
+void mulu64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b);
int divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor);
int divs128(int64_t *plow, int64_t *phigh, int64_t divisor);
--
2.23.0
^ permalink raw reply related [flat|nested] 24+ messages in thread* Re: [PATCH v4 09/11] fix the prototype of muls64/mulu64
2020-07-01 23:43 ` [PATCH v4 09/11] fix the prototype of muls64/mulu64 Lijun Pan
@ 2020-07-06 16:14 ` Laurent Vivier
0 siblings, 0 replies; 24+ messages in thread
From: Laurent Vivier @ 2020-07-06 16:14 UTC (permalink / raw)
To: Lijun Pan, qemu-ppc, qemu-devel; +Cc: richard.henderson, david
Le 02/07/2020 à 01:43, Lijun Pan a écrit :
> The prototypes of muls64/mulu64 in host-utils.h should match the
> definitions in host-utils.c
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
> ---
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> no change since v1
>
> include/qemu/host-utils.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h
> index 4cd170e6cd..cdca2991d8 100644
> --- a/include/qemu/host-utils.h
> +++ b/include/qemu/host-utils.h
> @@ -77,8 +77,8 @@ static inline int divs128(int64_t *plow, int64_t *phigh, int64_t divisor)
> }
> }
> #else
> -void muls64(uint64_t *phigh, uint64_t *plow, int64_t a, int64_t b);
> -void mulu64(uint64_t *phigh, uint64_t *plow, uint64_t a, uint64_t b);
> +void muls64(uint64_t *plow, uint64_t *phigh, int64_t a, int64_t b);
> +void mulu64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b);
> int divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor);
> int divs128(int64_t *plow, int64_t *phigh, int64_t divisor);
>
>
Applied to my trivial-patches-for-5.1 branch.
Thanks,
Laurent
^ permalink raw reply [flat|nested] 24+ messages in thread
* Re: [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions
2020-07-01 23:43 [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
` (8 preceding siblings ...)
2020-07-01 23:43 ` [PATCH v4 09/11] fix the prototype of muls64/mulu64 Lijun Pan
@ 2020-07-05 9:10 ` David Gibson
2020-07-06 7:34 ` Greg Kurz
9 siblings, 1 reply; 24+ messages in thread
From: David Gibson @ 2020-07-05 9:10 UTC (permalink / raw)
To: Lijun Pan; +Cc: richard.henderson, qemu-ppc, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1768 bytes --]
On Wed, Jul 01, 2020 at 06:43:35PM -0500, Lijun Pan wrote:
> This patch series add several newly introduced 32/64-bit vector
> instructions in Power ISA 3.1. Power ISA 3.1 flag is introduced in
> this version. In v4 version, coding style issues are fixed, community
> reviews/suggestions are taken into consideration.
So, is the ISA 3.1 document available somewhere?
>
> Lijun Pan (11):
> target/ppc: Introduce Power ISA 3.1 flag
> target/ppc: Enable Power ISA 3.1
> target/ppc: add byte-reverse br[dwh] instructions
> target/ppc: convert vmuluwm to tcg_gen_gvec_mul
> target/ppc: add vmulld instruction
> Update PowerPC AT_HWCAP2 definition
> target/ppc: add vmulld to INDEX_op_mul_vec case
> target/ppc: add vmulh{su}w instructions
> fix the prototype of muls64/mulu64
> target/ppc: add vmulh{su}d instructions
> target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions
>
> include/elf.h | 1 +
> include/qemu/host-utils.h | 4 +-
> target/ppc/cpu.h | 4 +-
> target/ppc/helper.h | 13 ++++-
> target/ppc/int_helper.c | 75 ++++++++++++++++++++++++-----
> target/ppc/translate.c | 43 +++++++++++++++++
> target/ppc/translate/vmx-impl.inc.c | 26 +++++++++-
> target/ppc/translate/vmx-ops.inc.c | 27 +++++++++--
> target/ppc/translate_init.inc.c | 2 +-
> tcg/ppc/tcg-target.h | 2 +
> tcg/ppc/tcg-target.inc.c | 12 ++++-
> 11 files changed, 184 insertions(+), 25 deletions(-)
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 24+ messages in thread* Re: [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions
2020-07-05 9:10 ` [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions David Gibson
@ 2020-07-06 7:34 ` Greg Kurz
0 siblings, 0 replies; 24+ messages in thread
From: Greg Kurz @ 2020-07-06 7:34 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, richard.henderson, Lijun Pan, qemu-devel
[-- Attachment #1: Type: text/plain, Size: 1883 bytes --]
On Sun, 5 Jul 2020 19:10:46 +1000
David Gibson <david@gibson.dropbear.id.au> wrote:
> On Wed, Jul 01, 2020 at 06:43:35PM -0500, Lijun Pan wrote:
> > This patch series add several newly introduced 32/64-bit vector
> > instructions in Power ISA 3.1. Power ISA 3.1 flag is introduced in
> > this version. In v4 version, coding style issues are fixed, community
> > reviews/suggestions are taken into consideration.
>
> So, is the ISA 3.1 document available somewhere?
>
In https://www-355.ibm.com/systems/power/openpower/ there's a link to
the PDF:
https://ibm.ent.box.com/s/hhjfw0x0lrbtyzmiaffnbxh2fuo0fog0
> >
> > Lijun Pan (11):
> > target/ppc: Introduce Power ISA 3.1 flag
> > target/ppc: Enable Power ISA 3.1
> > target/ppc: add byte-reverse br[dwh] instructions
> > target/ppc: convert vmuluwm to tcg_gen_gvec_mul
> > target/ppc: add vmulld instruction
> > Update PowerPC AT_HWCAP2 definition
> > target/ppc: add vmulld to INDEX_op_mul_vec case
> > target/ppc: add vmulh{su}w instructions
> > fix the prototype of muls64/mulu64
> > target/ppc: add vmulh{su}d instructions
> > target/ppc: add vdiv{su}{wd} vmod{su}{wd} instructions
> >
> > include/elf.h | 1 +
> > include/qemu/host-utils.h | 4 +-
> > target/ppc/cpu.h | 4 +-
> > target/ppc/helper.h | 13 ++++-
> > target/ppc/int_helper.c | 75 ++++++++++++++++++++++++-----
> > target/ppc/translate.c | 43 +++++++++++++++++
> > target/ppc/translate/vmx-impl.inc.c | 26 +++++++++-
> > target/ppc/translate/vmx-ops.inc.c | 27 +++++++++--
> > target/ppc/translate_init.inc.c | 2 +-
> > tcg/ppc/tcg-target.h | 2 +
> > tcg/ppc/tcg-target.inc.c | 12 ++++-
> > 11 files changed, 184 insertions(+), 25 deletions(-)
> >
>
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^ permalink raw reply [flat|nested] 24+ messages in thread