From: Thomas Huth <huth@tuxfamily.org>
To: qemu-devel@nongnu.org, "Michael Rolnik" <mrolnik@gmail.com>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Richard Henderson" <rth@twiddle.net>
Cc: Sarah Harris <S.E.Harris@kent.ac.uk>
Subject: [PATCH rc6 05/30] target/avr: CPU class: Add migration support
Date: Sun, 5 Jul 2020 16:02:50 +0200 [thread overview]
Message-ID: <20200705140315.260514-6-huth@tuxfamily.org> (raw)
In-Reply-To: <20200705140315.260514-1-huth@tuxfamily.org>
From: Michael Rolnik <mrolnik@gmail.com>
Add migration-related functions of AVR CPU class object.
[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Co-developed-by: Michael Rolnik <mrolnik@gmail.com>
Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk>
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
---
target/avr/cpu.c | 1 +
target/avr/cpu.h | 2 +
target/avr/machine.c | 121 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 124 insertions(+)
create mode 100644 target/avr/machine.c
diff --git a/target/avr/cpu.c b/target/avr/cpu.c
index a1d5f3c1eb..ced1107824 100644
--- a/target/avr/cpu.c
+++ b/target/avr/cpu.c
@@ -206,6 +206,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data)
cc->memory_rw_debug = avr_cpu_memory_rw_debug;
cc->get_phys_page_debug = avr_cpu_get_phys_page_debug;
cc->tlb_fill = avr_cpu_tlb_fill;
+ cc->vmsd = &vms_avr_cpu;
cc->disas_set_info = avr_cpu_disas_set_info;
cc->tcg_initialize = avr_cpu_tcg_init;
cc->synchronize_from_tb = avr_cpu_synchronize_from_tb;
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
index ac14e642bf..d3003f8e25 100644
--- a/target/avr/cpu.h
+++ b/target/avr/cpu.h
@@ -118,6 +118,8 @@ typedef struct AVRCPU {
CPUAVRState env;
} AVRCPU;
+extern const struct VMStateDescription vms_avr_cpu;
+
void avr_cpu_do_interrupt(CPUState *cpu);
bool avr_cpu_exec_interrupt(CPUState *cpu, int int_req);
hwaddr avr_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
diff --git a/target/avr/machine.c b/target/avr/machine.c
new file mode 100644
index 0000000000..ba44bd042b
--- /dev/null
+++ b/target/avr/machine.c
@@ -0,0 +1,121 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2019 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "migration/cpu.h"
+
+static int get_sreg(QEMUFile *f, void *opaque, size_t size,
+ const VMStateField *field)
+{
+ CPUAVRState *env = opaque;
+ uint8_t sreg;
+
+ sreg = qemu_get_byte(f);
+ cpu_set_sreg(env, sreg);
+ return 0;
+}
+
+static int put_sreg(
+ QEMUFile *f, void *opaque, size_t size,
+ const VMStateField *field, QJSON *vmdesc)
+{
+ CPUAVRState *env = opaque;
+ uint8_t sreg = cpu_get_sreg(env);
+
+ qemu_put_byte(f, sreg);
+ return 0;
+}
+
+static const VMStateInfo vms_sreg = {
+ .name = "sreg",
+ .get = get_sreg,
+ .put = put_sreg,
+};
+
+static int get_segment(
+ QEMUFile *f, void *opaque, size_t size, const VMStateField *field)
+{
+ uint32_t *ramp = opaque;
+ uint8_t temp;
+
+ temp = qemu_get_byte(f);
+ *ramp = ((uint32_t)temp) << 16;
+ return 0;
+}
+
+static int put_segment(
+ QEMUFile *f, void *opaque, size_t size,
+ const VMStateField *field, QJSON *vmdesc)
+{
+ uint32_t *ramp = opaque;
+ uint8_t temp = *ramp >> 16;
+
+ qemu_put_byte(f, temp);
+ return 0;
+}
+
+static const VMStateInfo vms_rampD = {
+ .name = "rampD",
+ .get = get_segment,
+ .put = put_segment,
+};
+static const VMStateInfo vms_rampX = {
+ .name = "rampX",
+ .get = get_segment,
+ .put = put_segment,
+};
+static const VMStateInfo vms_rampY = {
+ .name = "rampY",
+ .get = get_segment,
+ .put = put_segment,
+};
+static const VMStateInfo vms_rampZ = {
+ .name = "rampZ",
+ .get = get_segment,
+ .put = put_segment,
+};
+static const VMStateInfo vms_eind = {
+ .name = "eind",
+ .get = get_segment,
+ .put = put_segment,
+};
+
+const VMStateDescription vms_avr_cpu = {
+ .name = "cpu",
+ .version_id = 0,
+ .minimum_version_id = 0,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(env.pc_w, AVRCPU),
+ VMSTATE_UINT32(env.sp, AVRCPU),
+ VMSTATE_UINT32(env.skip, AVRCPU),
+
+ VMSTATE_UINT32_ARRAY(env.r, AVRCPU, NUMBER_OF_CPU_REGISTERS),
+
+ VMSTATE_SINGLE(env, AVRCPU, 0, vms_sreg, CPUAVRState),
+ VMSTATE_SINGLE(env.rampD, AVRCPU, 0, vms_rampD, uint32_t),
+ VMSTATE_SINGLE(env.rampX, AVRCPU, 0, vms_rampX, uint32_t),
+ VMSTATE_SINGLE(env.rampY, AVRCPU, 0, vms_rampY, uint32_t),
+ VMSTATE_SINGLE(env.rampZ, AVRCPU, 0, vms_rampZ, uint32_t),
+ VMSTATE_SINGLE(env.eind, AVRCPU, 0, vms_eind, uint32_t),
+
+ VMSTATE_END_OF_LIST()
+ }
+};
--
2.26.2
next prev parent reply other threads:[~2020-07-05 14:06 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-05 14:02 [PATCH rc6 00/30] target/avr merger Thomas Huth
2020-07-05 14:02 ` [PATCH rc6 01/30] target/avr: Add basic parameters of the new platform Thomas Huth
2020-07-05 14:02 ` [PATCH rc6 02/30] target/avr: Introduce basic CPU class object Thomas Huth
2020-07-05 14:02 ` [PATCH rc6 03/30] target/avr: CPU class: Add interrupt handling support Thomas Huth
2020-07-05 14:02 ` [PATCH rc6 04/30] target/avr: CPU class: Add memory menagement support Thomas Huth
2020-07-05 14:02 ` Thomas Huth [this message]
2020-07-05 14:02 ` [PATCH rc6 06/30] target/avr: CPU class: Add GDB support Thomas Huth
2020-07-05 14:02 ` [PATCH rc6 07/30] target/avr: Introduce enumeration AVRFeature Thomas Huth
2020-07-05 14:02 ` [PATCH rc6 08/30] target/avr: Add defintions of AVR core types Thomas Huth
2020-07-05 14:02 ` [PATCH rc6 09/30] target/avr: Add instruction helpers Thomas Huth
2020-07-05 14:02 ` [PATCH rc6 10/30] target/avr: Add instruction translation - Register definitions Thomas Huth
2020-07-05 14:02 ` [PATCH rc6 11/30] target/avr: Add instruction translation - Arithmetic and Logic Instructions Thomas Huth
2020-07-05 14:02 ` [PATCH rc6 12/30] target/avr: Add instruction translation - Branch Instructions Thomas Huth
2020-07-05 14:02 ` [PATCH rc6 13/30] target/avr: Add instruction translation - Data Transfer Instructions Thomas Huth
2020-07-05 14:02 ` [PATCH rc6 14/30] target/avr: Add instruction translation - Bit and Bit-test Instructions Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 15/30] target/avr: Add instruction translation - MCU Control Instructions Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 16/30] target/avr: Add instruction translation - CPU main translation function Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 17/30] target/avr: Initialize TCG register variables Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 18/30] target/avr: Add support for disassembling via option '-d in_asm' Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 19/30] hw/char: avr: Add limited support for USART peripheral Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 20/30] hw/timer: avr: Add limited support for 16-bit timer peripheral Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 21/30] hw/misc: avr: Add limited support for power reduction device Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 22/30] target/avr: Register AVR support with the rest of QEMU Thomas Huth
2020-07-06 14:56 ` Eric Blake
2020-07-06 16:36 ` Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 23/30] hw/avr: Add support for loading ELF/raw binaries Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 24/30] hw/avr: Add some ATmega microcontrollers Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 25/30] hw/avr: Add limited support for some Arduino boards Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 26/30] target/avr: Update build system Thomas Huth
2020-07-05 21:30 ` Philippe Mathieu-Daudé
2020-07-05 14:03 ` [PATCH rc6 27/30] tests/machine-none: Add AVR support Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 28/30] tests/boot-serial: Test some Arduino boards (AVR based) Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 29/30] tests/acceptance: Test the Arduino MEGA2560 board Thomas Huth
2020-07-05 14:03 ` [PATCH rc6 30/30] target/avr: Add section into QEMU documentation Thomas Huth
2020-07-05 14:29 ` [PATCH rc6 00/30] target/avr merger no-reply
2020-07-05 18:30 ` Thomas Huth
2020-07-05 18:42 ` Peter Maydell
2020-07-07 17:57 ` Philippe Mathieu-Daudé
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