From: Peter Xu <peterx@redhat.com>
To: Liu Yi L <yi.l.liu@intel.com>
Cc: jasowang@redhat.com, qemu-devel@nongnu.org, mst@redhat.com
Subject: Re: [PATCH] intel_iommu: Use correct shift for 256 bits qi descriptor
Date: Mon, 6 Jul 2020 16:58:19 -0400 [thread overview]
Message-ID: <20200706205819.GC88106@xz-x1> (raw)
In-Reply-To: <1593850035-35483-1-git-send-email-yi.l.liu@intel.com>
On Sat, Jul 04, 2020 at 01:07:15AM -0700, Liu Yi L wrote:
> In chapter 10.4.23 of VT-d spec 3.0, Descriptor Width bit was introduced
> in VTD_IQA_REG. Sfotware could set this bit to tell VT-d the QI descriptor
> from software would be 256 bits. Accordingly, the VTD_IQH_QH_SHIFT should
> be 5 when descriptor size is 256 bits.
>
> This patch adds the DW bit check when deciding the shift used to update
> VTD_IQH_REG.
>
> Signed-off-by: Liu Yi L <yi.l.liu@intel.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
--
Peter Xu
next prev parent reply other threads:[~2020-07-06 20:59 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-04 8:07 [PATCH] intel_iommu: Use correct shift for 256 bits qi descriptor Liu Yi L
2020-07-06 20:58 ` Peter Xu [this message]
2020-07-07 2:24 ` Liu, Yi L
2020-07-07 9:17 ` Jason Wang
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