From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: Max Filippov <jcmvbkbc@gmail.com>
Subject: [PATCH 15/21] tests/tcg/xtensa: update test_fp1 for DFPU
Date: Mon, 6 Jul 2020 16:47:31 -0700 [thread overview]
Message-ID: <20200706234737.32378-16-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com>
DFPU sets Invalid flag in FSR when at least one argument of FP
comparison opcodes is NaN, SNaN for most opcodes, any NaN for olt/ole.
Add checks for FSR and expected FSR values.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/test_fp1.S | 62 ++++++++++++++++++++-----------------
1 file changed, 34 insertions(+), 28 deletions(-)
diff --git a/tests/tcg/xtensa/test_fp1.S b/tests/tcg/xtensa/test_fp1.S
index 6e182e5964bd..77336a3fcf2c 100644
--- a/tests/tcg/xtensa/test_fp1.S
+++ b/tests/tcg/xtensa/test_fp1.S
@@ -1,4 +1,5 @@
#include "macros.inc"
+#include "fpu.h"
test_suite fp1
@@ -9,7 +10,7 @@ test_suite fp1
wfr \fr, a2
.endm
-.macro test_ord_ex op, br, fr0, fr1, v0, v1, r
+.macro test_ord_ex op, br, fr0, fr1, v0, v1, r, sr
movi a2, 0
wur a2, fsr
movfp \fr0, \v0
@@ -20,65 +21,70 @@ test_suite fp1
movt a2, a3, \br
assert eqi, a2, \r
rur a2, fsr
+#if DFPU
+ movi a3, \sr
+ assert eq, a2, a3
+#else
assert eqi, a2, 0
+#endif
.endm
-.macro test_ord op, br, fr0, fr1, v0, v1, r
+.macro test_ord op, br, fr0, fr1, v0, v1, r, sr
movi a2, 0
wur a2, fcr
- test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r
+ test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr
movi a2, 0x7c
wur a2, fcr
- test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r
+ test_ord_ex \op, \br, \fr0, \fr1, \v0, \v1, \r, \sr
.endm
-.macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI
- test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa
- test_ord \op b1, f2, f3, 0x3f800000, 0x3fc00000, \ab
- test_ord \op b2, f4, f5, 0x3fc00000, 0x3f800000, \ba
- test_ord \op b3, f6, f7, 0x3f800000, 0x7f800000, \aPI
- test_ord \op b4, f8, f9, 0x7f800000, 0x3f800000, \PIa
- test_ord \op b5, f10, f11, 0x3f800000, 0xffc00001, \aN
- test_ord \op b6, f12, f13, 0x3f800000, 0xff800001, \aN
- test_ord \op b7, f14, f15, 0x3f800000, 0x7f800001, \aN
- test_ord \op b8, f0, f1, 0x3f800000, 0x7fc00000, \aN
- test_ord \op b9, f2, f3, 0xffc00001, 0x3f800000, \Na
- test_ord \op b10, f4, f5, 0xff800001, 0x3f800000, \Na
- test_ord \op b11, f6, f7, 0x7f800001, 0x3f800000, \Na
- test_ord \op b12, f8, f9, 0x7fc00000, 0x3f800000, \Na
- test_ord \op b13, f10, f11, 0x7f800000, 0x7f800000, \II
- test_ord \op b14, f12, f13, 0x7f800000, 0x7fc00000, \IN
- test_ord \op b15, f14, f15, 0x7fc00000, 0x7f800000, \NI
+.macro test_ord_all op, aa, ab, ba, aPI, PIa, aN, Na, II, IN, NI, qnan_sr
+ test_ord \op b0, f0, f1, 0x3f800000, 0x3f800000, \aa, FSR__ /* ord == ord */
+ test_ord \op b1, f2, f3, 0x3f800000, 0x3fc00000, \ab, FSR__ /* ord < ord */
+ test_ord \op b2, f4, f5, 0x3fc00000, 0x3f800000, \ba, FSR__ /* ord > ord */
+ test_ord \op b3, f6, f7, 0x3f800000, 0x7f800000, \aPI, FSR__ /* ord +INF */
+ test_ord \op b4, f8, f9, 0x7f800000, 0x3f800000, \PIa, FSR__ /* +INF ord */
+ test_ord \op b5, f10, f11, 0x3f800000, 0xffc00001, \aN, \qnan_sr /* ord -QNaN */
+ test_ord \op b6, f12, f13, 0x3f800000, 0xff800001, \aN, FSR_V /* ord -SNaN */
+ test_ord \op b7, f14, f15, 0x3f800000, 0x7f800001, \aN, FSR_V /* ord +SNaN */
+ test_ord \op b8, f0, f1, 0x3f800000, 0x7fc00000, \aN, \qnan_sr /* ord +QNaN */
+ test_ord \op b9, f2, f3, 0xffc00001, 0x3f800000, \Na, \qnan_sr /* -QNaN ord */
+ test_ord \op b10, f4, f5, 0xff800001, 0x3f800000, \Na, FSR_V /* -SNaN ord */
+ test_ord \op b11, f6, f7, 0x7f800001, 0x3f800000, \Na, FSR_V /* +SNaN ord */
+ test_ord \op b12, f8, f9, 0x7fc00000, 0x3f800000, \Na, \qnan_sr /* +QNaN ord */
+ test_ord \op b13, f10, f11, 0x7f800000, 0x7f800000, \II, FSR__ /* +INF +INF */
+ test_ord \op b14, f12, f13, 0x7f800000, 0x7fc00000, \IN, \qnan_sr /* +INF +QNaN */
+ test_ord \op b15, f14, f15, 0x7fc00000, 0x7f800000, \NI, \qnan_sr /* +QNaN +INF */
.endm
test un_s
movi a2, 1
wsr a2, cpenable
- test_ord_all un.s, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1
+ test_ord_all un.s, 0, 0, 0, 0, 0, 1, 1, 0, 1, 1, FSR__
test_end
test oeq_s
- test_ord_all oeq.s, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0
+ test_ord_all oeq.s, 1, 0, 0, 0, 0, 0, 0, 1, 0, 0, FSR__
test_end
test ueq_s
- test_ord_all ueq.s, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1
+ test_ord_all ueq.s, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, FSR__
test_end
test olt_s
- test_ord_all olt.s, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0
+ test_ord_all olt.s, 0, 1, 0, 1, 0, 0, 0, 0, 0, 0, FSR_V
test_end
test ult_s
- test_ord_all ult.s, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1
+ test_ord_all ult.s, 0, 1, 0, 1, 0, 1, 1, 0, 1, 1, FSR__
test_end
test ole_s
- test_ord_all ole.s, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0
+ test_ord_all ole.s, 1, 1, 0, 1, 0, 0, 0, 1, 0, 0, FSR_V
test_end
test ule_s
- test_ord_all ule.s, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1
+ test_ord_all ule.s, 1, 1, 0, 1, 0, 1, 1, 1, 1, 1, FSR__
test_end
.macro test_cond op, fr0, fr1, cr, v0, v1, r
--
2.20.1
next prev parent reply other threads:[~2020-07-06 23:57 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-06 23:47 [PATCH 00/21] target/xtensa: implement double precision FPU Max Filippov
2020-07-06 23:47 ` [PATCH 01/21] softfloat: make NO_SIGNALING_NANS runtime property Max Filippov
2020-07-07 10:28 ` Alex Bennée
2020-07-08 17:41 ` Philippe Mathieu-Daudé
2020-07-06 23:47 ` [PATCH 02/21] softfloat: pass float_status pointer to pickNaN Max Filippov
2020-07-07 10:29 ` Alex Bennée
2020-07-06 23:47 ` [PATCH 03/21] softfloat: add xtensa specialization for pickNaNMulAdd Max Filippov
2020-07-07 10:29 ` Alex Bennée
2020-07-08 16:07 ` Richard Henderson
2020-07-08 18:11 ` Max Filippov
2020-07-06 23:47 ` [PATCH 04/21] target/xtensa: add geometry to xtensa_get_regfile_by_name Max Filippov
2020-07-06 23:47 ` [PATCH 05/21] target/xtensa: support copying registers up to 64 bits wide Max Filippov
2020-07-08 16:14 ` Richard Henderson
2020-07-08 17:14 ` Max Filippov
2020-07-06 23:47 ` [PATCH 06/21] target/xtensa: rename FPU2000 translators and helpers Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 07/21] target/xtensa: move FSR/FCR register accessors Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 08/21] target/xtensa: don't access BR regfile directly Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 09/21] target/xtensa: add DFP option, registers and opcodes Max Filippov
2020-07-08 16:25 ` Richard Henderson
2020-07-08 17:37 ` Max Filippov
2020-07-09 0:19 ` Richard Henderson
2020-07-09 5:14 ` Max Filippov
2020-07-06 23:47 ` [PATCH 10/21] target/xtensa: implement FPU division and square root Max Filippov
2020-07-06 23:47 ` [PATCH 11/21] tests/tcg/xtensa: fix test execution on ISS Max Filippov
2020-07-06 23:47 ` [PATCH 12/21] tests/tcg/xtensa: update test_fp0_arith for DFPU Max Filippov
2020-07-06 23:47 ` [PATCH 13/21] tests/tcg/xtensa: expand madd tests Max Filippov
2020-07-06 23:47 ` [PATCH 14/21] tests/tcg/xtensa: update test_fp0_conv for DFPU Max Filippov
2020-07-06 23:47 ` Max Filippov [this message]
2020-07-06 23:47 ` [PATCH 16/21] tests/tcg/xtensa: update test_lsc " Max Filippov
2020-07-06 23:47 ` [PATCH 17/21] tests/tcg/xtensa: add fp0 div and sqrt tests Max Filippov
2020-07-06 23:47 ` [PATCH 18/21] tests/tcg/xtensa: test double precision load/store Max Filippov
2020-07-06 23:47 ` [PATCH 19/21] tests/tcg/xtensa: add DFP0 arith tests Max Filippov
2020-07-06 23:47 ` [PATCH 20/21] target/xtensa: import DE_233L_FPU core Max Filippov
2020-07-06 23:47 ` [PATCH 21/21] target/xtensa: import DSP3400 core Max Filippov
2020-07-07 11:31 ` [PATCH 00/21] target/xtensa: implement double precision FPU Alex Bennée
2020-07-07 16:56 ` Max Filippov
2020-07-07 19:21 ` Alex Bennée
2020-07-07 23:14 ` Max Filippov
2020-07-08 8:50 ` Alex Bennée
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