From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: Max Filippov <jcmvbkbc@gmail.com>
Subject: [PATCH 16/21] tests/tcg/xtensa: update test_lsc for DFPU
Date: Mon, 6 Jul 2020 16:47:32 -0700 [thread overview]
Message-ID: <20200706234737.32378-17-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com>
DFPU doesn't have pre-increment FP load/store opcodes, it has
post-increment opcodes instead. Test increment opcodes present in the
current config.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/test_lsc.S | 47 +++++++++++++++++++++++++++----------
1 file changed, 34 insertions(+), 13 deletions(-)
diff --git a/tests/tcg/xtensa/test_lsc.S b/tests/tcg/xtensa/test_lsc.S
index 0578bf19e72e..9d59c1815a9e 100644
--- a/tests/tcg/xtensa/test_lsc.S
+++ b/tests/tcg/xtensa/test_lsc.S
@@ -1,4 +1,5 @@
#include "macros.inc"
+#include "fpu.h"
test_suite lsc
@@ -9,9 +10,14 @@ test lsi
wsr a2, cpenable
movi a2, 1f
- lsi f0, a2, 0
lsi f1, a2, 4
+#if DFPU
+ lsi f2, a2, 8
+ lsip f0, a2, 8
+#else
+ lsi f0, a2, 0
lsiu f2, a2, 8
+#endif
movi a3, 1f + 8
assert eq, a2, a3
rfr a2, f0
@@ -34,13 +40,18 @@ test ssi
movi a2, 1f
movi a3, 0x40800000
wfr f3, a3
- ssi f3, a2, 0
movi a3, 0x40a00000
wfr f4, a3
- ssi f4, a2, 4
movi a3, 0x40c00000
wfr f5, a3
+ ssi f4, a2, 4
+#if DFPU
+ ssi f5, a2, 8
+ ssip f3, a2, 8
+#else
+ ssi f3, a2, 0
ssiu f5, a2, 8
+#endif
movi a3, 1f + 8
assert eq, a2, a3
l32i a4, a2, -8
@@ -62,11 +73,16 @@ test_end
test lsx
movi a2, 1f
movi a3, 0
+ movi a4, 4
+ movi a5, 8
+ lsx f7, a2, a4
+#if DFPU
+ lsx f8, a2, a5
+ lsxp f6, a2, a5
+#else
lsx f6, a2, a3
- movi a3, 4
- lsx f7, a2, a3
- movi a3, 8
- lsxu f8, a2, a3
+ lsxu f8, a2, a5
+#endif
movi a3, 1f + 8
assert eq, a2, a3
rfr a2, f6
@@ -87,18 +103,23 @@ test_end
test ssx
movi a2, 1f
- movi a3, 0
movi a4, 0x41200000
wfr f9, a4
- ssx f9, a2, a3
- movi a3, 4
movi a4, 0x41300000
wfr f10, a4
- ssx f10, a2, a3
- movi a3, 8
movi a4, 0x41400000
wfr f11, a4
- ssxu f11, a2, a3
+ movi a3, 0
+ movi a4, 4
+ movi a5, 8
+ ssx f10, a2, a4
+#if DFPU
+ ssx f11, a2, a5
+ ssxp f9, a2, a5
+#else
+ ssx f9, a2, a3
+ ssxu f11, a2, a5
+#endif
movi a3, 1f + 8
assert eq, a2, a3
l32i a4, a2, -8
--
2.20.1
next prev parent reply other threads:[~2020-07-06 23:55 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-06 23:47 [PATCH 00/21] target/xtensa: implement double precision FPU Max Filippov
2020-07-06 23:47 ` [PATCH 01/21] softfloat: make NO_SIGNALING_NANS runtime property Max Filippov
2020-07-07 10:28 ` Alex Bennée
2020-07-08 17:41 ` Philippe Mathieu-Daudé
2020-07-06 23:47 ` [PATCH 02/21] softfloat: pass float_status pointer to pickNaN Max Filippov
2020-07-07 10:29 ` Alex Bennée
2020-07-06 23:47 ` [PATCH 03/21] softfloat: add xtensa specialization for pickNaNMulAdd Max Filippov
2020-07-07 10:29 ` Alex Bennée
2020-07-08 16:07 ` Richard Henderson
2020-07-08 18:11 ` Max Filippov
2020-07-06 23:47 ` [PATCH 04/21] target/xtensa: add geometry to xtensa_get_regfile_by_name Max Filippov
2020-07-06 23:47 ` [PATCH 05/21] target/xtensa: support copying registers up to 64 bits wide Max Filippov
2020-07-08 16:14 ` Richard Henderson
2020-07-08 17:14 ` Max Filippov
2020-07-06 23:47 ` [PATCH 06/21] target/xtensa: rename FPU2000 translators and helpers Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 07/21] target/xtensa: move FSR/FCR register accessors Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 08/21] target/xtensa: don't access BR regfile directly Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 09/21] target/xtensa: add DFP option, registers and opcodes Max Filippov
2020-07-08 16:25 ` Richard Henderson
2020-07-08 17:37 ` Max Filippov
2020-07-09 0:19 ` Richard Henderson
2020-07-09 5:14 ` Max Filippov
2020-07-06 23:47 ` [PATCH 10/21] target/xtensa: implement FPU division and square root Max Filippov
2020-07-06 23:47 ` [PATCH 11/21] tests/tcg/xtensa: fix test execution on ISS Max Filippov
2020-07-06 23:47 ` [PATCH 12/21] tests/tcg/xtensa: update test_fp0_arith for DFPU Max Filippov
2020-07-06 23:47 ` [PATCH 13/21] tests/tcg/xtensa: expand madd tests Max Filippov
2020-07-06 23:47 ` [PATCH 14/21] tests/tcg/xtensa: update test_fp0_conv for DFPU Max Filippov
2020-07-06 23:47 ` [PATCH 15/21] tests/tcg/xtensa: update test_fp1 " Max Filippov
2020-07-06 23:47 ` Max Filippov [this message]
2020-07-06 23:47 ` [PATCH 17/21] tests/tcg/xtensa: add fp0 div and sqrt tests Max Filippov
2020-07-06 23:47 ` [PATCH 18/21] tests/tcg/xtensa: test double precision load/store Max Filippov
2020-07-06 23:47 ` [PATCH 19/21] tests/tcg/xtensa: add DFP0 arith tests Max Filippov
2020-07-06 23:47 ` [PATCH 20/21] target/xtensa: import DE_233L_FPU core Max Filippov
2020-07-06 23:47 ` [PATCH 21/21] target/xtensa: import DSP3400 core Max Filippov
2020-07-07 11:31 ` [PATCH 00/21] target/xtensa: implement double precision FPU Alex Bennée
2020-07-07 16:56 ` Max Filippov
2020-07-07 19:21 ` Alex Bennée
2020-07-07 23:14 ` Max Filippov
2020-07-08 8:50 ` Alex Bennée
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200706234737.32378-17-jcmvbkbc@gmail.com \
--to=jcmvbkbc@gmail.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).