From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: Max Filippov <jcmvbkbc@gmail.com>
Subject: [PATCH 17/21] tests/tcg/xtensa: add fp0 div and sqrt tests
Date: Mon, 6 Jul 2020 16:47:33 -0700 [thread overview]
Message-ID: <20200706234737.32378-18-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com>
Test exact division/sqrt DFPU sequences.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/test_fp0_div.S | 82 ++++++++++++++++++++++++++++++++
tests/tcg/xtensa/test_fp0_sqrt.S | 76 +++++++++++++++++++++++++++++
2 files changed, 158 insertions(+)
create mode 100644 tests/tcg/xtensa/test_fp0_div.S
create mode 100644 tests/tcg/xtensa/test_fp0_sqrt.S
diff --git a/tests/tcg/xtensa/test_fp0_div.S b/tests/tcg/xtensa/test_fp0_div.S
new file mode 100644
index 000000000000..c3e7ad7bb5b3
--- /dev/null
+++ b/tests/tcg/xtensa/test_fp0_div.S
@@ -0,0 +1,82 @@
+#include "macros.inc"
+#include "fpu.h"
+
+test_suite fp0_div
+
+#if XCHAL_HAVE_FP_DIV
+
+.macro divs_seq q, a, b, r, y, y0, an, bn, e, ex
+ div0.s \y0, \b
+ nexp01.s \bn, \b
+ const.s \e, 1
+ maddn.s \e, \bn, \y0
+ mov.s \y, \y0
+ mov.s \ex, \b
+ nexp01.s \an, \a
+ maddn.s \y, \e, \y0
+ const.s \e, 1
+ const.s \q, 0
+ neg.s \r, \an
+ maddn.s \e, \bn, \y
+ maddn.s \q, \r, \y0
+ mkdadj.s \ex, \a
+ maddn.s \y, \e, \y
+ maddn.s \r, \bn, \q
+ const.s \e, 1
+ maddn.s \e, \bn, \y
+ maddn.s \q, \r, \y
+ neg.s \r, \an
+ maddn.s \y, \e, \y
+ maddn.s \r, \bn, \q
+ addexpm.s \q, \ex
+ addexp.s \y, \ex
+ divn.s \q, \r, \y
+.endm
+
+.macro div_s fr0, fr1, fr2
+ divs_seq \fr0, \fr1, \fr2, f9, f10, f11, f12, f13, f14, f15
+.endm
+
+.macro movfp fr, v
+ movi a2, \v
+ wfr \fr, a2
+.endm
+
+.macro check_res fr, r, sr
+ rfr a2, \fr
+ dump a2
+ movi a3, \r
+ assert eq, a2, a3
+ rur a2, fsr
+ movi a3, \sr
+ assert eq, a2, a3
+.endm
+
+test div_s
+ movi a2, 1
+ wsr a2, cpenable
+
+ test_op2 div_s, f0, f1, f2, 0x40000000, 0x40400000, \
+ 0x3f2aaaab, 0x3f2aaaaa, 0x3f2aaaab, 0x3f2aaaaa, \
+ FSR_I, FSR_I, FSR_I, FSR_I
+ test_op2 div_s, f3, f4, f5, F32_1, F32_0, \
+ F32_PINF, F32_PINF, F32_PINF, F32_PINF, \
+ FSR_Z, FSR_Z, FSR_Z, FSR_Z
+ test_op2 div_s, f6, f7, f8, F32_0, F32_0, \
+ F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \
+ FSR_V, FSR_V, FSR_V, FSR_V
+
+ /* MAX_FLOAT / 0.5 = +inf/MAX_FLOAT */
+ test_op2 div_s, f0, f1, f2, F32_MAX, F32_0_5, \
+ F32_PINF, F32_MAX, F32_PINF, F32_MAX, \
+ FSR_OI, FSR_OI, FSR_OI, FSR_OI
+
+ /* 0.5 / MAX_FLOAT = denorm */
+ test_op2 div_s, f0, f1, f2, F32_0_5, F32_MAX, \
+ 0x00100000, 0x00100000, 0x00100001, 0x00100000, \
+ FSR_UI, FSR_UI, FSR_UI, FSR_UI
+test_end
+
+#endif
+
+test_suite_end
diff --git a/tests/tcg/xtensa/test_fp0_sqrt.S b/tests/tcg/xtensa/test_fp0_sqrt.S
new file mode 100644
index 000000000000..585973dce6bc
--- /dev/null
+++ b/tests/tcg/xtensa/test_fp0_sqrt.S
@@ -0,0 +1,76 @@
+#include "macros.inc"
+#include "fpu.h"
+
+test_suite fp0_sqrt
+
+#if XCHAL_HAVE_FP_SQRT
+
+.macro sqrt_seq r, a, y, t1, hn, h2, t5, h
+ sqrt0.s \y, \a
+ const.s \t1, 0
+ maddn.s \t1, \y, \y
+ nexp01.s \hn, \a
+ const.s \r, 3
+ addexp.s \hn, \r
+ maddn.s \r, \t1, \hn
+ nexp01.s \t1, \a
+ neg.s \h2, \t1
+ maddn.s \y, \r, \y
+ const.s \r, 0
+ const.s \t5, 0
+ const.s \h, 0
+ maddn.s \r, \h2, \y
+ maddn.s \t5, \y, \hn
+ const.s \hn, 3
+ maddn.s \h, \hn, \y
+ maddn.s \t1, \r, \r
+ maddn.s \hn, \t5, \y
+ neg.s \y, \h
+ maddn.s \r, \t1, \y
+ maddn.s \h, \hn, \h
+ mksadj.s \y, \a
+ nexp01.s \a, \a
+ maddn.s \a, \r, \r
+ neg.s \t1, \h
+ addexpm.s \r, \y
+ addexp.s \t1, \y
+ divn.s \r, \a, \t1
+.endm
+
+.macro sqrt_s fr0, fr1
+ sqrt_seq \fr0, \fr1, f10, f11, f12, f13, f14, f15
+.endm
+
+.macro movfp fr, v
+ movi a2, \v
+ wfr \fr, a2
+.endm
+
+.macro check_res fr, r, sr
+ rfr a2, \fr
+ dump a2
+ movi a3, \r
+ assert eq, a2, a3
+ rur a2, fsr
+ movi a3, \sr
+ assert eq, a2, a3
+.endm
+
+test sqrt_s
+ movi a2, 1
+ wsr a2, cpenable
+
+ test_op1 sqrt_s, f0, f1, 0x40000000, \
+ 0x3fb504f3, 0x3fb504f3, 0x3fb504f4, 0x3fb504f3, \
+ FSR_I, FSR_I, FSR_I, FSR_I
+ test_op1 sqrt_s, f3, f4, F32_1, \
+ F32_1, F32_1, F32_1, F32_1, \
+ FSR__, FSR__, FSR__, FSR__
+ test_op1 sqrt_s, f6, f7, F32_MINUS | F32_1, \
+ F32_DNAN, F32_DNAN, F32_DNAN, F32_DNAN, \
+ FSR_V, FSR_V, FSR_V, FSR_V
+test_end
+
+#endif
+
+test_suite_end
--
2.20.1
next prev parent reply other threads:[~2020-07-06 23:56 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-06 23:47 [PATCH 00/21] target/xtensa: implement double precision FPU Max Filippov
2020-07-06 23:47 ` [PATCH 01/21] softfloat: make NO_SIGNALING_NANS runtime property Max Filippov
2020-07-07 10:28 ` Alex Bennée
2020-07-08 17:41 ` Philippe Mathieu-Daudé
2020-07-06 23:47 ` [PATCH 02/21] softfloat: pass float_status pointer to pickNaN Max Filippov
2020-07-07 10:29 ` Alex Bennée
2020-07-06 23:47 ` [PATCH 03/21] softfloat: add xtensa specialization for pickNaNMulAdd Max Filippov
2020-07-07 10:29 ` Alex Bennée
2020-07-08 16:07 ` Richard Henderson
2020-07-08 18:11 ` Max Filippov
2020-07-06 23:47 ` [PATCH 04/21] target/xtensa: add geometry to xtensa_get_regfile_by_name Max Filippov
2020-07-06 23:47 ` [PATCH 05/21] target/xtensa: support copying registers up to 64 bits wide Max Filippov
2020-07-08 16:14 ` Richard Henderson
2020-07-08 17:14 ` Max Filippov
2020-07-06 23:47 ` [PATCH 06/21] target/xtensa: rename FPU2000 translators and helpers Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 07/21] target/xtensa: move FSR/FCR register accessors Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 08/21] target/xtensa: don't access BR regfile directly Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 09/21] target/xtensa: add DFP option, registers and opcodes Max Filippov
2020-07-08 16:25 ` Richard Henderson
2020-07-08 17:37 ` Max Filippov
2020-07-09 0:19 ` Richard Henderson
2020-07-09 5:14 ` Max Filippov
2020-07-06 23:47 ` [PATCH 10/21] target/xtensa: implement FPU division and square root Max Filippov
2020-07-06 23:47 ` [PATCH 11/21] tests/tcg/xtensa: fix test execution on ISS Max Filippov
2020-07-06 23:47 ` [PATCH 12/21] tests/tcg/xtensa: update test_fp0_arith for DFPU Max Filippov
2020-07-06 23:47 ` [PATCH 13/21] tests/tcg/xtensa: expand madd tests Max Filippov
2020-07-06 23:47 ` [PATCH 14/21] tests/tcg/xtensa: update test_fp0_conv for DFPU Max Filippov
2020-07-06 23:47 ` [PATCH 15/21] tests/tcg/xtensa: update test_fp1 " Max Filippov
2020-07-06 23:47 ` [PATCH 16/21] tests/tcg/xtensa: update test_lsc " Max Filippov
2020-07-06 23:47 ` Max Filippov [this message]
2020-07-06 23:47 ` [PATCH 18/21] tests/tcg/xtensa: test double precision load/store Max Filippov
2020-07-06 23:47 ` [PATCH 19/21] tests/tcg/xtensa: add DFP0 arith tests Max Filippov
2020-07-06 23:47 ` [PATCH 20/21] target/xtensa: import DE_233L_FPU core Max Filippov
2020-07-06 23:47 ` [PATCH 21/21] target/xtensa: import DSP3400 core Max Filippov
2020-07-07 11:31 ` [PATCH 00/21] target/xtensa: implement double precision FPU Alex Bennée
2020-07-07 16:56 ` Max Filippov
2020-07-07 19:21 ` Alex Bennée
2020-07-07 23:14 ` Max Filippov
2020-07-08 8:50 ` Alex Bennée
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