From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: Max Filippov <jcmvbkbc@gmail.com>
Subject: [PATCH 19/21] tests/tcg/xtensa: add DFP0 arith tests
Date: Mon, 6 Jul 2020 16:47:35 -0700 [thread overview]
Message-ID: <20200706234737.32378-20-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <20200706234737.32378-1-jcmvbkbc@gmail.com>
Add test for basic double precision opcode properties.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/test_dfp0_arith.S | 153 +++++++++++++++++++++++++++++
1 file changed, 153 insertions(+)
create mode 100644 tests/tcg/xtensa/test_dfp0_arith.S
diff --git a/tests/tcg/xtensa/test_dfp0_arith.S b/tests/tcg/xtensa/test_dfp0_arith.S
new file mode 100644
index 000000000000..f2c72f97938d
--- /dev/null
+++ b/tests/tcg/xtensa/test_dfp0_arith.S
@@ -0,0 +1,153 @@
+#include "macros.inc"
+#include "fpu.h"
+
+test_suite fp0_arith
+
+#if XCHAL_HAVE_DFP
+
+.macro movfp fr, v
+ movi a2, ((\v) >> 32) & 0xffffffff
+ movi a3, ((\v) & 0xffffffff)
+ wfrd \fr, a2, a3
+.endm
+
+.macro check_res fr, r, sr
+ rfrd a2, \fr
+ dump a2
+ movi a3, ((\r) >> 32) & 0xffffffff
+ assert eq, a2, a3
+ rfr a2, \fr
+ dump a2
+ movi a3, ((\r) & 0xffffffff)
+ assert eq, a2, a3
+ rur a2, fsr
+ movi a3, \sr
+ assert eq, a2, a3
+.endm
+
+test add_d
+ movi a2, 1
+ wsr a2, cpenable
+
+ /* MAX_FLOAT + MAX_FLOAT = +inf/MAX_FLOAT */
+ test_op2 add.d, f6, f7, f8, F64_MAX, F64_MAX, \
+ F64_PINF, F64_MAX, F64_PINF, F64_MAX, \
+ FSR_OI, FSR_OI, FSR_OI, FSR_OI
+test_end
+
+test add_d_inf
+ /* 1 + +inf = +inf */
+ test_op2 add.d, f6, f7, f8, F64_1, F64_PINF, \
+ F64_PINF, F64_PINF, F64_PINF, F64_PINF, \
+ FSR__, FSR__, FSR__, FSR__
+
+ /* +inf + -inf = default NaN */
+ test_op2 add.d, f0, f1, f2, F64_PINF, F64_NINF, \
+ F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \
+ FSR_V, FSR_V, FSR_V, FSR_V
+test_end
+
+test add_d_nan_dfpu
+ /* 1 + QNaN = QNaN */
+ test_op2 add.d, f9, f10, f11, F64_1, F64_QNAN(1), \
+ F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
+ FSR__, FSR__, FSR__, FSR__
+ /* 1 + SNaN = QNaN */
+ test_op2 add.d, f12, f13, f14, F64_1, F64_SNAN(1), \
+ F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
+ FSR_V, FSR_V, FSR_V, FSR_V
+
+ /* SNaN1 + SNaN2 = QNaN2 */
+ test_op2 add.d, f15, f0, f1, F64_SNAN(1), F64_SNAN(2), \
+ F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
+ FSR_V, FSR_V, FSR_V, FSR_V
+ /* QNaN1 + SNaN2 = QNaN2 */
+ test_op2 add.d, f5, f6, f7, F64_QNAN(1), F64_SNAN(2), \
+ F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
+ FSR_V, FSR_V, FSR_V, FSR_V
+ /* SNaN1 + QNaN2 = QNaN2 */
+ test_op2 add.d, f8, f9, f10, F64_SNAN(1), F64_QNAN(2), \
+ F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
+ FSR_V, FSR_V, FSR_V, FSR_V
+test_end
+
+test sub_s
+ /* norm - norm = denorm */
+ test_op2 sub.d, f6, f7, f8, F64_MIN_NORM | 1, F64_MIN_NORM, \
+ 0x00000001, 0x00000001, 0x00000001, 0x00000001, \
+ FSR__, FSR__, FSR__, FSR__
+test_end
+
+test mul_s
+ test_op2 mul.d, f0, f1, f2, F64_1 | 1, F64_1 | 1, \
+ F64_1 | 2, F64_1 | 2, F64_1 | 3, F64_1 | 2, \
+ FSR_I, FSR_I, FSR_I, FSR_I
+ /* MAX_FLOAT/2 * MAX_FLOAT/2 = +inf/MAX_FLOAT */
+ test_op2 mul.d, f6, f7, f8, F64_MAX_2, F64_MAX_2, \
+ F64_PINF, F64_MAX, F64_PINF, F64_MAX, \
+ FSR_OI, FSR_OI, FSR_OI, FSR_OI
+ /* min norm * min norm = 0/denorm */
+ test_op2 mul.d, f6, f7, f8, F64_MIN_NORM, F64_MIN_NORM, \
+ F64_0, F64_0, 0x00000001, F64_0, \
+ FSR_UI, FSR_UI, FSR_UI, FSR_UI
+ /* inf * 0 = default NaN */
+ test_op2 mul.d, f6, f7, f8, F64_PINF, F64_0, \
+ F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \
+ FSR_V, FSR_V, FSR_V, FSR_V
+test_end
+
+test madd_d
+ test_op3 madd.d, f0, f1, f2, f0, F64_0, F64_1 | 1, F64_1 | 1, \
+ F64_1 | 2, F64_1 | 2, F64_1 | 3, F64_1 | 2, \
+ FSR_I, FSR_I, FSR_I, FSR_I
+test_end
+
+test madd_d_precision
+ test_op3 madd.d, f0, f1, f2, f0, \
+ F64_MINUS | F64_1 | 2, F64_1 | 1, F64_1 | 1, \
+ 0x3970000000000000, 0x3970000000000000, 0x3970000000000000, 0x3970000000000000, \
+ FSR__, FSR__, FSR__, FSR__
+test_end
+
+test madd_d_nan_dfpu
+ /* DFPU madd/msub NaN1, NaN2, NaN3 priority: NaN1, NaN3, NaN2 */
+ test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_1, F64_1, \
+ F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
+ FSR__, FSR__, FSR__, FSR__
+ test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_QNAN(2), F64_1, \
+ F64_QNAN(2), F64_QNAN(2), F64_QNAN(2), F64_QNAN(2), \
+ FSR__, FSR__, FSR__, FSR__
+ test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_1, F64_QNAN(3), \
+ F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), \
+ FSR__, FSR__, FSR__, FSR__
+
+ test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_QNAN(2), F64_1, \
+ F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
+ FSR__, FSR__, FSR__, FSR__
+ test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_1, F64_QNAN(3), \
+ F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
+ FSR__, FSR__, FSR__, FSR__
+ test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_QNAN(2), F64_QNAN(3), \
+ F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), F64_QNAN(3), \
+ FSR__, FSR__, FSR__, FSR__
+ test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_QNAN(2), F64_QNAN(3), \
+ F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
+ FSR__, FSR__, FSR__, FSR__
+
+ /* inf * 0 = default NaN */
+ test_op3 madd.d, f0, f1, f2, f0, F64_1, F64_PINF, F64_0, \
+ F64_DNAN, F64_DNAN, F64_DNAN, F64_DNAN, \
+ FSR_V, FSR_V, FSR_V, FSR_V
+
+ /* madd/msub SNaN turns to QNaN and sets Invalid flag */
+ test_op3 madd.d, f0, f1, f2, f0, F64_SNAN(1), F64_1, F64_1, \
+ F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
+ FSR_V, FSR_V, FSR_V, FSR_V
+ test_op3 madd.d, f0, f1, f2, f0, F64_QNAN(1), F64_SNAN(2), F64_1, \
+ F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), F64_QNAN(1), \
+ FSR_V, FSR_V, FSR_V, FSR_V
+test_end
+
+#endif
+
+test_suite_end
--
2.20.1
next prev parent reply other threads:[~2020-07-06 23:59 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-06 23:47 [PATCH 00/21] target/xtensa: implement double precision FPU Max Filippov
2020-07-06 23:47 ` [PATCH 01/21] softfloat: make NO_SIGNALING_NANS runtime property Max Filippov
2020-07-07 10:28 ` Alex Bennée
2020-07-08 17:41 ` Philippe Mathieu-Daudé
2020-07-06 23:47 ` [PATCH 02/21] softfloat: pass float_status pointer to pickNaN Max Filippov
2020-07-07 10:29 ` Alex Bennée
2020-07-06 23:47 ` [PATCH 03/21] softfloat: add xtensa specialization for pickNaNMulAdd Max Filippov
2020-07-07 10:29 ` Alex Bennée
2020-07-08 16:07 ` Richard Henderson
2020-07-08 18:11 ` Max Filippov
2020-07-06 23:47 ` [PATCH 04/21] target/xtensa: add geometry to xtensa_get_regfile_by_name Max Filippov
2020-07-06 23:47 ` [PATCH 05/21] target/xtensa: support copying registers up to 64 bits wide Max Filippov
2020-07-08 16:14 ` Richard Henderson
2020-07-08 17:14 ` Max Filippov
2020-07-06 23:47 ` [PATCH 06/21] target/xtensa: rename FPU2000 translators and helpers Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 07/21] target/xtensa: move FSR/FCR register accessors Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 08/21] target/xtensa: don't access BR regfile directly Max Filippov
2020-07-08 16:18 ` Richard Henderson
2020-07-06 23:47 ` [PATCH 09/21] target/xtensa: add DFP option, registers and opcodes Max Filippov
2020-07-08 16:25 ` Richard Henderson
2020-07-08 17:37 ` Max Filippov
2020-07-09 0:19 ` Richard Henderson
2020-07-09 5:14 ` Max Filippov
2020-07-06 23:47 ` [PATCH 10/21] target/xtensa: implement FPU division and square root Max Filippov
2020-07-06 23:47 ` [PATCH 11/21] tests/tcg/xtensa: fix test execution on ISS Max Filippov
2020-07-06 23:47 ` [PATCH 12/21] tests/tcg/xtensa: update test_fp0_arith for DFPU Max Filippov
2020-07-06 23:47 ` [PATCH 13/21] tests/tcg/xtensa: expand madd tests Max Filippov
2020-07-06 23:47 ` [PATCH 14/21] tests/tcg/xtensa: update test_fp0_conv for DFPU Max Filippov
2020-07-06 23:47 ` [PATCH 15/21] tests/tcg/xtensa: update test_fp1 " Max Filippov
2020-07-06 23:47 ` [PATCH 16/21] tests/tcg/xtensa: update test_lsc " Max Filippov
2020-07-06 23:47 ` [PATCH 17/21] tests/tcg/xtensa: add fp0 div and sqrt tests Max Filippov
2020-07-06 23:47 ` [PATCH 18/21] tests/tcg/xtensa: test double precision load/store Max Filippov
2020-07-06 23:47 ` Max Filippov [this message]
2020-07-06 23:47 ` [PATCH 20/21] target/xtensa: import DE_233L_FPU core Max Filippov
2020-07-06 23:47 ` [PATCH 21/21] target/xtensa: import DSP3400 core Max Filippov
2020-07-07 11:31 ` [PATCH 00/21] target/xtensa: implement double precision FPU Alex Bennée
2020-07-07 16:56 ` Max Filippov
2020-07-07 19:21 ` Alex Bennée
2020-07-07 23:14 ` Max Filippov
2020-07-08 8:50 ` Alex Bennée
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200706234737.32378-20-jcmvbkbc@gmail.com \
--to=jcmvbkbc@gmail.com \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).