From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Sarah Harris" <S.E.Harris@kent.ac.uk>,
"Thomas Huth" <huth@tuxfamily.org>,
"Joaquin de Andres" <me@xcancerberox.com.ar>,
"Richard Henderson" <richard.henderson@linaro.org>,
"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
"Michael Rolnik" <mrolnik@gmail.com>
Subject: [RFC PATCH 3/3] target/avr: Fix SBRC/SBRS instructions
Date: Tue, 7 Jul 2020 08:46:46 +0200 [thread overview]
Message-ID: <20200707064646.7603-4-f4bug@amsat.org> (raw)
In-Reply-To: <20200707064646.7603-1-f4bug@amsat.org>
SBRC/SBRS instructions seem to be inverted.
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
target/avr/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index fe03e676df..2f77fe3ba7 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -1385,7 +1385,7 @@ static bool trans_SBRC(DisasContext *ctx, arg_SBRC *a)
{
TCGv Rr = cpu_r[a->rr];
- ctx->skip_cond = TCG_COND_EQ;
+ ctx->skip_cond = TCG_COND_NE;
ctx->skip_var0 = tcg_temp_new();
ctx->free_skip_var0 = true;
@@ -1401,7 +1401,7 @@ static bool trans_SBRS(DisasContext *ctx, arg_SBRS *a)
{
TCGv Rr = cpu_r[a->rr];
- ctx->skip_cond = TCG_COND_NE;
+ ctx->skip_cond = TCG_COND_EQ;
ctx->skip_var0 = tcg_temp_new();
ctx->free_skip_var0 = true;
--
2.21.3
next prev parent reply other threads:[~2020-07-07 6:50 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-07 6:46 [PATCH 0/3] target/avr: Few fixes Philippe Mathieu-Daudé
2020-07-07 6:46 ` [PATCH 1/3] target/avr: Drop tlb_flush() in avr_cpu_reset() Philippe Mathieu-Daudé
2020-07-07 8:27 ` Alex Bennée
2020-07-07 6:46 ` [PATCH 2/3] target/avr: Fix $PC displayed address Philippe Mathieu-Daudé
2020-07-07 8:33 ` Alex Bennée
2020-07-07 6:46 ` Philippe Mathieu-Daudé [this message]
2020-07-07 8:56 ` [RFC PATCH 3/3] target/avr: Fix SBRC/SBRS instructions Alex Bennée
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