From: David Gibson <david@gibson.dropbear.id.au>
To: Lijun Pan <ljp@linux.ibm.com>
Cc: richard.henderson@linaro.org, qemu-ppc@nongnu.org, qemu-devel@nongnu.org
Subject: Re: [PATCH v4 03/11] target/ppc: add byte-reverse br[dwh] instructions
Date: Tue, 7 Jul 2020 20:30:46 +1000 [thread overview]
Message-ID: <20200707103046.GE18595@umbus.fritz.box> (raw)
In-Reply-To: <20200701234344.91843-4-ljp@linux.ibm.com>
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On Wed, Jul 01, 2020 at 06:43:38PM -0500, Lijun Pan wrote:
> POWER ISA 3.1 introduces following byte-reverse instructions:
> brd: Byte-Reverse Doubleword X-form
> brw: Byte-Reverse Word X-form
> brh: Byte-Reverse Halfword X-form
>
> Signed-off-by: Lijun Pan <ljp@linux.ibm.com>
Applied to ppc-for-5.2.
> ---
> v4: make it compile on all targets
> v3: fix the store issue in br[dwh]
> simplify brw implementation
> add "if defined(TARGET_PPC64)"
> v2: fix coding style
> use Power ISA 3.1 flag
>
> target/ppc/translate.c | 40 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 40 insertions(+)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 4ce3d664b5..590c3e3bc7 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -6971,7 +6971,47 @@ static void gen_dform3D(DisasContext *ctx)
> return gen_invalid(ctx);
> }
>
> +#if defined(TARGET_PPC64)
> +/* brd */
> +static void gen_brd(DisasContext *ctx)
> +{
> + tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
> +}
> +
> +/* brw */
> +static void gen_brw(DisasContext *ctx)
> +{
> + tcg_gen_bswap64_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
> + tcg_gen_rotli_i64(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 32);
> +
> +}
> +
> +/* brh */
> +static void gen_brh(DisasContext *ctx)
> +{
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + TCGv_i64 t1 = tcg_temp_new_i64();
> + TCGv_i64 t2 = tcg_temp_new_i64();
> +
> + tcg_gen_movi_i64(t0, 0x00ff00ff00ff00ffull);
> + tcg_gen_shri_i64(t1, cpu_gpr[rS(ctx->opcode)], 8);
> + tcg_gen_and_i64(t2, t1, t0);
> + tcg_gen_and_i64(t1, cpu_gpr[rS(ctx->opcode)], t0);
> + tcg_gen_shli_i64(t1, t1, 8);
> + tcg_gen_or_i64(cpu_gpr[rA(ctx->opcode)], t1, t2);
> +
> + tcg_temp_free_i64(t0);
> + tcg_temp_free_i64(t1);
> + tcg_temp_free_i64(t2);
> +}
> +#endif
> +
> static opcode_t opcodes[] = {
> +#if defined(TARGET_PPC64)
> +GEN_HANDLER_E(brd, 0x1F, 0x1B, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA310),
> +GEN_HANDLER_E(brw, 0x1F, 0x1B, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA310),
> +GEN_HANDLER_E(brh, 0x1F, 0x1B, 0x06, 0x0000F801, PPC_NONE, PPC2_ISA310),
> +#endif
> GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
> GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
> GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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next prev parent reply other threads:[~2020-07-07 10:33 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-01 23:43 [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions Lijun Pan
2020-07-01 23:43 ` [PATCH v4 01/11] target/ppc: Introduce Power ISA 3.1 flag Lijun Pan
2020-07-05 9:07 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 02/11] target/ppc: Enable Power ISA 3.1 Lijun Pan
2020-07-05 9:08 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 03/11] target/ppc: add byte-reverse br[dwh] instructions Lijun Pan
2020-07-07 10:30 ` David Gibson [this message]
2020-07-01 23:43 ` [PATCH v4 04/11] target/ppc: convert vmuluwm to tcg_gen_gvec_mul Lijun Pan
2020-07-08 12:22 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 05/11] target/ppc: add vmulld instruction Lijun Pan
2020-07-13 5:11 ` David Gibson
2020-07-01 23:43 ` [PATCH v4 06/11] Update PowerPC AT_HWCAP2 definition Lijun Pan
2020-07-13 5:14 ` David Gibson
2020-07-13 19:20 ` Lijun Pan
2020-07-13 23:47 ` David Gibson
2020-07-14 20:28 ` Lijun Pan
2020-07-01 23:43 ` [PATCH v4 07/11] target/ppc: add vmulld to INDEX_op_mul_vec case Lijun Pan
2020-07-13 19:40 ` Lijun Pan
2020-07-01 23:43 ` [PATCH v4 08/11] target/ppc: add vmulh{su}w instructions Lijun Pan
2020-07-13 19:35 ` Lijun Pan
2020-07-01 23:43 ` [PATCH v4 09/11] fix the prototype of muls64/mulu64 Lijun Pan
2020-07-06 16:14 ` Laurent Vivier
2020-07-05 9:10 ` [PATCH v4 00/11] Add several Power ISA 3.1 32/64-bit vector instructions David Gibson
2020-07-06 7:34 ` Greg Kurz
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