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[81.231.232.130]) by smtp.gmail.com with ESMTPSA id m2sm134736ljc.58.2020.07.07.05.28.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Jul 2020 05:28:13 -0700 (PDT) Date: Tue, 7 Jul 2020 14:28:49 +0200 From: "Edgar E. Iglesias" To: Vikram Garhwal Subject: Re: [PATCH v7 2/4] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers Message-ID: <20200707122849.GA4114@toto> References: <1593113607-321118-1-git-send-email-fnu.vikram@xilinx.com> <1593113607-321118-3-git-send-email-fnu.vikram@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1593113607-321118-3-git-send-email-fnu.vikram@xilinx.com> User-Agent: Mutt/1.10.1 (2018-07-13) Received-SPF: pass client-ip=2a00:1450:4864:20::143; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x143.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: francisco.iglesias@xilinx.com, Alistair Francis , qemu-devel@nongnu.org, "open list:Xilinx ZynqMP" , Peter Maydell Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Thu, Jun 25, 2020 at 12:33:25PM -0700, Vikram Garhwal wrote: > Connect CAN0 and CAN1 on the ZynqMP. > > Acked-by: Alistair Francis Reviewed-by: Edgar E. Iglesias > Signed-off-by: Vikram Garhwal > --- > hw/arm/xlnx-zynqmp.c | 28 ++++++++++++++++++++++++++++ > include/hw/arm/xlnx-zynqmp.h | 4 ++++ > 2 files changed, 32 insertions(+) > > diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c > index 1de9d4a..3f93524 100644 > --- a/hw/arm/xlnx-zynqmp.c > +++ b/hw/arm/xlnx-zynqmp.c > @@ -81,6 +81,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] = { > 21, 22, > }; > > +static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] = { > + 0xFF060000, 0xFF070000, > +}; > + > +static const int can_intr[XLNX_ZYNQMP_NUM_CAN] = { > + 23, 24, > +}; > + > static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] = { > 0xFF160000, 0xFF170000, > }; > @@ -247,6 +255,11 @@ static void xlnx_zynqmp_init(Object *obj) > TYPE_CADENCE_UART); > } > > + for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { > + object_initialize_child(obj, "can[*]", &s->can[i], > + TYPE_XLNX_ZYNQMP_CAN); > + } > + > object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); > > for (i = 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { > @@ -492,6 +505,21 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) > gic_spi[uart_intr[i]]); > } > > + for (i = 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { > + object_property_set_int(OBJECT(&s->can[i]), i, "ctrl-idx", > + &error_abort); > + object_property_set_int(OBJECT(&s->can[i]), XLNX_ZYNQMP_CAN_REF_CLK, > + "ext_clk_freq", &error_abort); > + sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err); > + if (err) { > + error_propagate(errp, err); > + return; > + } > + sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]); > + sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0, > + gic_spi[can_intr[i]]); > + } > + > object_property_set_int(OBJECT(&s->sata), SATA_NUM_PORTS, "num-ports", > &error_abort); > sysbus_realize(SYS_BUS_DEVICE(&s->sata), &err); > diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h > index 53076fa..dcb88e0 100644 > --- a/include/hw/arm/xlnx-zynqmp.h > +++ b/include/hw/arm/xlnx-zynqmp.h > @@ -22,6 +22,7 @@ > #include "hw/intc/arm_gic.h" > #include "hw/net/cadence_gem.h" > #include "hw/char/cadence_uart.h" > +#include "hw/net/xlnx-zynqmp-can.h" > #include "hw/ide/ahci.h" > #include "hw/sd/sdhci.h" > #include "hw/ssi/xilinx_spips.h" > @@ -41,6 +42,8 @@ > #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 > #define XLNX_ZYNQMP_NUM_GEMS 4 > #define XLNX_ZYNQMP_NUM_UARTS 2 > +#define XLNX_ZYNQMP_NUM_CAN 2 > +#define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000) > #define XLNX_ZYNQMP_NUM_SDHCI 2 > #define XLNX_ZYNQMP_NUM_SPIS 2 > #define XLNX_ZYNQMP_NUM_GDMA_CH 8 > @@ -92,6 +95,7 @@ typedef struct XlnxZynqMPState { > > CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; > CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; > + XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN]; > SysbusAHCIState sata; > SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; > XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; > -- > 2.7.4 >