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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Laurent Vivier" <lvivier@redhat.com>,
	"Sarah Harris" <S.E.Harris@kent.ac.uk>,
	"Eduardo Habkost" <ehabkost@redhat.com>,
	"Igor Mammedov" <imammedo@redhat.com>,
	"Thomas Huth" <huth@tuxfamily.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Cleber Rosa" <crosa@redhat.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Markus Armbruster" <armbru@redhat.com>,
	"Wainer dos Santos Moschetta" <wainersm@redhat.com>,
	"Thomas Huth" <thuth@redhat.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Michael Rolnik" <mrolnik@gmail.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Pavel Dovgalyuk" <pavel.dovgaluk@ispras.ru>,
	"Marc-André Lureau" <marcandre.lureau@redhat.com>,
	"Philippe Mathieu-Daudé" <philmd@redhat.com>,
	"Aleksandar Markovic" <aleksandar.m.mail@gmail.com>,
	"Richard Henderson" <rth@twiddle.net>
Subject: [PULL 01/32] target/avr: Add basic parameters of the new platform
Date: Tue,  7 Jul 2020 20:16:39 +0200	[thread overview]
Message-ID: <20200707181710.30950-2-f4bug@amsat.org> (raw)
In-Reply-To: <20200707181710.30950-1-f4bug@amsat.org>

From: Michael Rolnik <mrolnik@gmail.com>

This includes definitions of various basic parameters needed
for integration of a new platform into QEMU.

[AM: Split a larger AVR introduction patch into logical units]
Suggested-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Co-developed-by: Michael Rolnik <mrolnik@gmail.com>
Co-developed-by: Sarah Harris <S.E.Harris@kent.ac.uk>
Signed-off-by: Michael Rolnik <mrolnik@gmail.com>
Signed-off-by: Sarah Harris <S.E.Harris@kent.ac.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Aleksandar Markovic <aleksandar.m.mail@gmail.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[thuth: Simplify MAINTAINERS right from the start]
Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Message-Id: <20200705140315.260514-2-huth@tuxfamily.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/avr/cpu-param.h | 36 +++++++++++++++++++++++
 target/avr/cpu.h       | 66 ++++++++++++++++++++++++++++++++++++++++++
 MAINTAINERS            |  6 ++++
 3 files changed, 108 insertions(+)
 create mode 100644 target/avr/cpu-param.h
 create mode 100644 target/avr/cpu.h

diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
new file mode 100644
index 0000000000..7ef4e7c679
--- /dev/null
+++ b/target/avr/cpu-param.h
@@ -0,0 +1,36 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2016-2020 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#ifndef AVR_CPU_PARAM_H
+#define AVR_CPU_PARAM_H
+
+#define TARGET_LONG_BITS 32
+/*
+ * TARGET_PAGE_BITS cannot be more than 8 bits because
+ * 1.  all IO registers occupy [0x0000 .. 0x00ff] address range, and they
+ *     should be implemented as a device and not memory
+ * 2.  SRAM starts at the address 0x0100
+ */
+#define TARGET_PAGE_BITS 8
+#define TARGET_PHYS_ADDR_SPACE_BITS 24
+#define TARGET_VIRT_ADDR_SPACE_BITS 24
+#define NB_MMU_MODES 2
+
+#endif
diff --git a/target/avr/cpu.h b/target/avr/cpu.h
new file mode 100644
index 0000000000..45a87c5452
--- /dev/null
+++ b/target/avr/cpu.h
@@ -0,0 +1,66 @@
+/*
+ * QEMU AVR CPU
+ *
+ * Copyright (c) 2016-2020 Michael Rolnik
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License as published by the Free Software Foundation; either
+ * version 2.1 of the License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, see
+ * <http://www.gnu.org/licenses/lgpl-2.1.html>
+ */
+
+#ifndef QEMU_AVR_CPU_H
+#define QEMU_AVR_CPU_H
+
+#include "exec/cpu-defs.h"
+
+#define TCG_GUEST_DEFAULT_MO 0
+
+/*
+ * AVR has two memory spaces, data & code.
+ * e.g. both have 0 address
+ * ST/LD instructions access data space
+ * LPM/SPM and instruction fetching access code memory space
+ */
+#define MMU_CODE_IDX 0
+#define MMU_DATA_IDX 1
+
+#define EXCP_RESET 1
+#define EXCP_INT(n) (EXCP_RESET + (n) + 1)
+
+/* Number of CPU registers */
+#define NUMBER_OF_CPU_REGISTERS 32
+/* Number of IO registers accessible by ld/st/in/out */
+#define NUMBER_OF_IO_REGISTERS 64
+
+/*
+ * Offsets of AVR memory regions in host memory space.
+ *
+ * This is needed because the AVR has separate code and data address
+ * spaces that both have start from zero but have to go somewhere in
+ * host memory.
+ *
+ * It's also useful to know where some things are, like the IO registers.
+ */
+/* Flash program memory */
+#define OFFSET_CODE 0x00000000
+/* CPU registers, IO registers, and SRAM */
+#define OFFSET_DATA 0x00800000
+/* CPU registers specifically, these are mapped at the start of data */
+#define OFFSET_CPU_REGISTERS OFFSET_DATA
+/*
+ * IO registers, including status register, stack pointer, and memory
+ * mapped peripherals, mapped just after CPU registers
+ */
+#define OFFSET_IO_REGISTERS (OFFSET_DATA + NUMBER_OF_CPU_REGISTERS)
+
+#endif /* !defined (QEMU_AVR_CPU_H) */
diff --git a/MAINTAINERS b/MAINTAINERS
index b6602dcde2..6a012646eb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -167,6 +167,12 @@ S: Maintained
 F: hw/arm/smmu*
 F: include/hw/arm/smmu*
 
+AVR TCG CPUs
+M: Michael Rolnik <mrolnik@gmail.com>
+R: Sarah Harris <S.E.Harris@kent.ac.uk>
+S: Maintained
+F: target/avr/
+
 CRIS TCG CPUs
 M: Edgar E. Iglesias <edgar.iglesias@gmail.com>
 S: Maintained
-- 
2.21.3



  reply	other threads:[~2020-07-07 18:18 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-07-07 18:16 [PULL 00/32] AVR port Philippe Mathieu-Daudé
2020-07-07 18:16 ` Philippe Mathieu-Daudé [this message]
2020-07-07 18:16 ` [PULL 02/32] target/avr: Introduce basic CPU class object Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 03/32] target/avr: CPU class: Add interrupt handling support Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 04/32] target/avr: CPU class: Add memory menagement support Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 05/32] target/avr: CPU class: Add migration support Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 06/32] target/avr: CPU class: Add GDB support Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 07/32] target/avr: Introduce enumeration AVRFeature Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 08/32] target/avr: Add definitions of AVR core types Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 09/32] target/avr: Add instruction helpers Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 10/32] target/avr: Add instruction translation - Register definitions Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 11/32] target/avr: Add instruction translation - Arithmetic and Logic Instructions Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 12/32] target/avr: Add instruction translation - Branch Instructions Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 13/32] target/avr: Add instruction translation - Data Transfer Instructions Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 14/32] target/avr: Add instruction translation - Bit and Bit-test Instructions Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 15/32] target/avr: Add instruction translation - MCU Control Instructions Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 16/32] target/avr: Add instruction translation - CPU main translation function Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 17/32] target/avr: Initialize TCG register variables Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 18/32] target/avr: Add support for disassembling via option '-d in_asm' Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 19/32] target/avr: Register AVR support with the rest of QEMU Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 20/32] tests/machine-none: Add AVR support Philippe Mathieu-Daudé
2020-07-07 18:16 ` [PULL 21/32] hw/char: avr: Add limited support for USART peripheral Philippe Mathieu-Daudé
2020-07-07 18:17 ` [PULL 22/32] hw/timer: avr: Add limited support for 16-bit timer peripheral Philippe Mathieu-Daudé
2020-07-07 18:17 ` [PULL 23/32] hw/misc: avr: Add limited support for power reduction device Philippe Mathieu-Daudé
2020-07-07 18:17 ` [PULL 24/32] hw/avr: Add support for loading ELF/raw binaries Philippe Mathieu-Daudé
2020-07-13 12:40   ` Peter Maydell
2020-07-14 15:09     ` Philippe Mathieu-Daudé
2020-07-07 18:17 ` [PULL 25/32] hw/avr: Add some ATmega microcontrollers Philippe Mathieu-Daudé
2020-07-07 18:17 ` [PULL 26/32] hw/avr: Add limited support for some Arduino boards Philippe Mathieu-Daudé
2020-07-07 18:17 ` [PULL 27/32] tests/boot-serial: Test some Arduino boards (AVR based) Philippe Mathieu-Daudé
2020-07-07 18:17 ` [PULL 28/32] tests/acceptance: Test the Arduino MEGA2560 board Philippe Mathieu-Daudé
2020-07-07 18:17 ` [PULL 29/32] target/avr: Add section into QEMU documentation Philippe Mathieu-Daudé
2020-07-07 18:17 ` [PULL 30/32] target/avr/cpu: Drop tlb_flush() in avr_cpu_reset() Philippe Mathieu-Daudé
2020-07-07 18:17 ` [PULL 31/32] target/avr/cpu: Fix $PC displayed address Philippe Mathieu-Daudé
2020-07-07 18:17 ` [PULL 32/32] target/avr/disas: Fix store instructions display order Philippe Mathieu-Daudé
2020-07-10 11:41 ` [PULL 00/32] AVR port Peter Maydell
2020-07-10 15:02   ` Thomas Huth
2020-07-10 15:12     ` Peter Maydell
2020-07-10 15:17       ` Philippe Mathieu-Daudé
2020-07-10 15:32         ` Philippe Mathieu-Daudé
2020-07-10 15:45           ` Thomas Huth
2020-07-10 15:54           ` Richard Henderson
2020-07-10 16:00             ` Philippe Mathieu-Daudé

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