From: Max Filippov <jcmvbkbc@gmail.com>
To: qemu-devel@nongnu.org
Cc: Max Filippov <jcmvbkbc@gmail.com>,
Richard Henderson <richard.henderson@linaro.org>
Subject: [PATCH v4 12/22] tests/tcg/xtensa: fix test execution on ISS
Date: Sat, 11 Jul 2020 04:06:47 -0700 [thread overview]
Message-ID: <20200711110655.20287-13-jcmvbkbc@gmail.com> (raw)
In-Reply-To: <20200711110655.20287-1-jcmvbkbc@gmail.com>
Space for test results may be allocated in IRAM which is only
word-accessible. Use full 32-bit words to access test results.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
---
tests/tcg/xtensa/macros.inc | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/xtensa/macros.inc b/tests/tcg/xtensa/macros.inc
index aa8f95bce879..f88937c7bf82 100644
--- a/tests/tcg/xtensa/macros.inc
+++ b/tests/tcg/xtensa/macros.inc
@@ -3,7 +3,7 @@
.macro test_suite name
.data
status: .word result
-result: .space 256
+result: .space 1024
.text
.global main
.align 4
@@ -25,9 +25,9 @@ main:
movi a3, 0
beqz a2, 2f
1:
- l8ui a1, a0, 0
+ l32i a1, a0, 0
or a3, a3, a1
- addi a0, a0, 1
+ addi a0, a0, 4
addi a2, a2, -1
bnez a2, 1b
2:
@@ -65,7 +65,7 @@ test_\name:
reset_ps
movi a2, status
l32i a3, a2, 0
- addi a3, a3, 1
+ addi a3, a3, 4
s32i a3, a2, 0
.endm
@@ -78,7 +78,7 @@ test_\name:
movi a2, status
l32i a2, a2, 0
movi a3, 1
- s8i a3, a2, 0
+ s32i a3, a2, 0
#ifdef DEBUG
print failed
#endif
--
2.20.1
next prev parent reply other threads:[~2020-07-11 11:14 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-11 11:06 [PATCH v4 00/22] target/xtensa: implement double precision FPU Max Filippov
2020-07-11 11:06 ` [PATCH v4 01/22] softfloat: make NO_SIGNALING_NANS runtime property Max Filippov
2020-07-11 11:06 ` [PATCH v4 02/22] softfloat: pass float_status pointer to pickNaN Max Filippov
2020-07-11 11:06 ` [PATCH v4 03/22] softfloat: add xtensa specialization for pickNaNMulAdd Max Filippov
2020-07-11 11:06 ` [PATCH v4 04/22] target/xtensa: add geometry to xtensa_get_regfile_by_name Max Filippov
2020-07-11 11:06 ` [PATCH v4 05/22] target/xtensa: support copying registers up to 64 bits wide Max Filippov
2020-07-11 11:06 ` [PATCH v4 06/22] target/xtensa: rename FPU2000 translators and helpers Max Filippov
2020-07-11 11:06 ` [PATCH v4 07/22] target/xtensa: move FSR/FCR register accessors Max Filippov
2020-07-11 11:06 ` [PATCH v4 08/22] target/xtensa: don't access BR regfile directly Max Filippov
2020-07-11 11:06 ` [PATCH v4 09/22] target/xtensa: add DFPU option Max Filippov
2020-07-11 11:06 ` [PATCH v4 10/22] target/xtensa: add DFPU registers and opcodes Max Filippov
2020-07-11 11:06 ` [PATCH v4 11/22] target/xtensa: implement FPU division and square root Max Filippov
2020-07-11 11:06 ` Max Filippov [this message]
2020-07-11 11:06 ` [PATCH v4 13/22] tests/tcg/xtensa: update test_fp0_arith for DFPU Max Filippov
2020-07-11 11:06 ` [PATCH v4 14/22] tests/tcg/xtensa: expand madd tests Max Filippov
2020-07-11 11:06 ` [PATCH v4 15/22] tests/tcg/xtensa: update test_fp0_conv for DFPU Max Filippov
2020-07-11 11:06 ` [PATCH v4 16/22] tests/tcg/xtensa: update test_fp1 " Max Filippov
2020-07-11 11:06 ` [PATCH v4 17/22] tests/tcg/xtensa: update test_lsc " Max Filippov
2020-07-11 11:06 ` [PATCH v4 18/22] tests/tcg/xtensa: add fp0 div and sqrt tests Max Filippov
2020-07-11 11:06 ` [PATCH v4 19/22] tests/tcg/xtensa: test double precision load/store Max Filippov
2020-07-11 11:06 ` [PATCH v4 20/22] tests/tcg/xtensa: add DFP0 arithmetic tests Max Filippov
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