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[79.180.10.140]) by smtp.gmail.com with ESMTPSA id r28sm27457519wrr.20.2020.07.14.01.39.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2020 01:39:56 -0700 (PDT) Date: Tue, 14 Jul 2020 04:39:53 -0400 From: "Michael S. Tsirkin" To: Igor Mammedov Subject: Re: [RFC PATCH 4/5] hw/i386/acpi-build: Turn off support of PCIe native hot-plug and SHPC in _OSC Message-ID: <20200714040118-mutt-send-email-mst@kernel.org> References: <20200708224615.114077-1-jusual@redhat.com> <20200708224615.114077-5-jusual@redhat.com> <20200713165654.1f78af8f@redhat.com> MIME-Version: 1.0 In-Reply-To: <20200713165654.1f78af8f@redhat.com> X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=205.139.110.61; envelope-from=mst@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/14 03:57:32 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Julia Suvorova , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, Jul 13, 2020 at 04:56:54PM +0200, Igor Mammedov wrote: > On Thu, 9 Jul 2020 00:46:14 +0200 > Julia Suvorova wrote: > > > Other methods may be used if the system is capable of this and the _OSC bit > > is set. Disable them explicitly to force ACPI PCI hot-plug use. The older > > versions will still use PCIe native. Do we need that later part btw? > > > > Signed-off-by: Julia Suvorova > > --- > > hw/i386/acpi-build.c | 12 ++++++++---- > > 1 file changed, 8 insertions(+), 4 deletions(-) > > > > diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c > > index 5c5ad88ad6..0e2891c3ea 100644 > > --- a/hw/i386/acpi-build.c > > +++ b/hw/i386/acpi-build.c > > @@ -1599,6 +1599,7 @@ static Aml *build_q35_osc_method(AcpiPmInfo *pm) > > Aml *method; > > Aml *a_cwd1 = aml_name("CDW1"); > > Aml *a_ctrl = aml_local(0); > > + unsigned osc_ctrl; > > > > method = aml_method("_OSC", 4, AML_NOTSERIALIZED); > > aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); > > @@ -1612,9 +1613,12 @@ static Aml *build_q35_osc_method(AcpiPmInfo *pm) > > > > /* > > * Always allow native PME, AER (no dependencies) > > - * Allow SHPC (PCI bridges can have SHPC controller) > > + * Need to disable native and SHPC hot-plug to use acpihp > > + * > > + * PCI Firmware Specification, Revision 3.2 I don't think you have to add a reference as part of this patchset. The spec in question documents _OSC so it's not a bad idea to add it, but it's a bit more work, e.g. we generally try to list the earliest spec that documents the given feature, since So I suspect this is 3.0 actually. > seems incomplete, were you going to point to a concrete chapter that requires this change? It doesn't as such. A better description would be: / * Guests seem to generally prefer native hotplug control. As we want them to * use ACPI, don't enable it. */ > > */ > > - aml_append(if_ctx, aml_and(a_ctrl, aml_int(0x1F), a_ctrl)); > > + osc_ctrl = pm->pcihp_bridge_en ? 0x1C : 0x1F; > Since you are touching this, how about converting this magic number to > something more readable? > i.e. > set_bit(ACPI_OSC_SHPC_EN, osc_ctrl) > or > osc_ctrl |= BIT(SOME_FEATURE) > ... if there is such a macro. If not I suspect it's better as a comment: 0x10 /* PCI Express Capability Structure control */ | 0x80 /* PCI Express Advanced Error Reporting control */ | 0x40 /* PCI Express Native Power Management Events control */ > > + aml_append(if_ctx, aml_and(a_ctrl, aml_int(osc_ctrl), a_ctrl)); > > > > if_ctx2 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(1)))); > > /* Unknown revision */ > > @@ -1696,7 +1700,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > > aml_append(dev, aml_name_decl("_ADR", aml_int(0))); > > aml_append(dev, aml_name_decl("_UID", aml_int(1))); > > - aml_append(dev, build_q35_osc_method()); > > + aml_append(dev, build_q35_osc_method(pm)); > > aml_append(sb_scope, dev); > > aml_append(dsdt, sb_scope); > > > > @@ -1771,7 +1775,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, > > if (pci_bus_is_express(bus)) { > > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); > > aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); > > - aml_append(dev, build_q35_osc_method()); > > + aml_append(dev, build_q35_osc_method(pm)); > > } else { > > aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); > > }