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[216.160.65.90]) by smtp.gmail.com with ESMTPSA id q20sm4224635pfn.111.2020.07.23.17.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Jul 2020 17:28:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison Date: Thu, 23 Jul 2020 17:28:00 -0700 Message-Id: <20200724002807.441147-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: frank.chang@sifive.com, alistair23@gmail.com, qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is my take on Liu Zhiwei's patch set: https://patchew.org/QEMU/20200626205917.4545-1-zhiwei_liu@c-sky.com This differs from Zhiwei's v1 in: * If a helper is involved, the helper does the boxing and unboxing. * Which leaves only LDW and FSGN*.S as the only instructions that are expanded inline which need to handle nanboxing. * All mention of RVD is dropped vs boxing. This means that an RVF-only cpu will still generate and check nanboxes into the 64-bit cpu_fpu slots. There should be no way an RVF-only cpu can generate an unboxed cpu_fpu value. This choice is made to speed up the common case: RVF+RVD, so that we do not have to check whether RVD is enabled. * The translate.c primitives take TCGv values rather than fpu regno, which will make it possible to use them with RVV, since v0.9 does proper nanboxing. * I have adjusted the current naming to be float32 specific ("*_s"), to avoid confusion with the float16 data type supported by RVV. r~ LIU Zhiwei (2): target/riscv: Clean up fmv.w.x target/riscv: check before allocating TCG temps Richard Henderson (5): target/riscv: Generate nanboxed results from fp helpers target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s target/riscv: Generate nanboxed results from trans_rvf.inc.c target/riscv: Check nanboxed inputs to fp helpers target/riscv: Check nanboxed inputs in trans_rvf.inc.c target/riscv/internals.h | 16 ++++ target/riscv/fpu_helper.c | 102 ++++++++++++++++-------- target/riscv/insn_trans/trans_rvd.inc.c | 8 +- target/riscv/insn_trans/trans_rvf.inc.c | 99 ++++++++++++++--------- target/riscv/translate.c | 29 +++++++ 5 files changed, 178 insertions(+), 76 deletions(-) -- 2.25.1