From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: frank.chang@sifive.com, alistair23@gmail.com,
qemu-riscv@nongnu.org, zhiwei_liu@c-sky.com
Subject: [PATCH v2 7/7] target/riscv: check before allocating TCG temps
Date: Thu, 23 Jul 2020 17:28:07 -0700 [thread overview]
Message-ID: <20200724002807.441147-8-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200724002807.441147-1-richard.henderson@linaro.org>
From: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200626205917.4545-5-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvd.inc.c | 8 ++++----
target/riscv/insn_trans/trans_rvf.inc.c | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
index ea1044f13b..4f832637fa 100644
--- a/target/riscv/insn_trans/trans_rvd.inc.c
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -20,10 +20,10 @@
static bool trans_fld(DisasContext *ctx, arg_fld *a)
{
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEQ);
@@ -35,10 +35,10 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
{
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
index 0d04677a02..16df9c5ee2 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -25,10 +25,10 @@
static bool trans_flw(DisasContext *ctx, arg_flw *a)
{
- TCGv t0 = tcg_temp_new();
- gen_get_gpr(t0, a->rs1);
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
+ TCGv t0 = tcg_temp_new();
+ gen_get_gpr(t0, a->rs1);
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], t0, ctx->mem_idx, MO_TEUL);
@@ -41,11 +41,11 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
{
+ REQUIRE_FPU;
+ REQUIRE_EXT(ctx, RVF);
TCGv t0 = tcg_temp_new();
gen_get_gpr(t0, a->rs1);
- REQUIRE_FPU;
- REQUIRE_EXT(ctx, RVF);
tcg_gen_addi_tl(t0, t0, a->imm);
tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
--
2.25.1
next prev parent reply other threads:[~2020-07-24 0:36 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-24 0:28 [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison Richard Henderson
2020-07-24 0:28 ` [PATCH v2 1/7] target/riscv: Generate nanboxed results from fp helpers Richard Henderson
2020-07-24 2:35 ` LIU Zhiwei
2020-07-24 3:55 ` Richard Henderson
2020-07-24 6:05 ` LIU Zhiwei
2020-08-06 6:09 ` Chih-Min Chao
2020-08-06 7:05 ` LIU Zhiwei
2020-08-06 8:42 ` Chih-Min Chao
2020-08-06 10:02 ` LIU Zhiwei
2020-07-24 0:28 ` [PATCH v2 2/7] target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s Richard Henderson
2020-07-24 2:39 ` LIU Zhiwei
2020-08-06 6:24 ` Chih-Min Chao
2020-07-24 0:28 ` [PATCH v2 3/7] target/riscv: Generate nanboxed results from trans_rvf.inc.c Richard Henderson
2020-07-24 2:41 ` LIU Zhiwei
2020-08-06 6:24 ` Chih-Min Chao
2020-07-24 0:28 ` [PATCH v2 4/7] target/riscv: Check nanboxed inputs to fp helpers Richard Henderson
2020-07-24 2:47 ` LIU Zhiwei
2020-07-24 3:59 ` Richard Henderson
2020-08-06 6:26 ` Chih-Min Chao
2020-07-24 0:28 ` [PATCH v2 5/7] target/riscv: Check nanboxed inputs in trans_rvf.inc.c Richard Henderson
2020-07-24 6:04 ` LIU Zhiwei
2020-08-06 6:27 ` Chih-Min Chao
2020-08-07 20:24 ` Chih-Min Chao
2020-08-08 14:18 ` LIU Zhiwei
2020-08-08 23:06 ` LIU Zhiwei
2020-07-24 0:28 ` [PATCH v2 6/7] target/riscv: Clean up fmv.w.x Richard Henderson
2020-08-06 6:28 ` Chih-Min Chao
2020-07-24 0:28 ` Richard Henderson [this message]
2020-08-06 6:28 ` [PATCH v2 7/7] target/riscv: check before allocating TCG temps Chih-Min Chao
2020-07-24 2:31 ` [PATCH v2 0/7] target/riscv: NaN-boxing for multiple precison LIU Zhiwei
2020-07-27 23:37 ` Alistair Francis
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