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Tsirkin" To: Jan Kiszka Subject: Re: [RFC] ivshmem v2: Shared memory device specification Message-ID: <20200727091802-mutt-send-email-mst@kernel.org> References: MIME-Version: 1.0 In-Reply-To: X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Received-SPF: pass client-ip=205.139.110.61; envelope-from=mst@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/27 01:46:13 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jailhouse , liang yan , Alex =?iso-8859-1?Q?Benn=E9e?= , qemu-devel , "virtio-comment@lists.oasis-open.org" Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On Mon, May 25, 2020 at 09:58:28AM +0200, Jan Kiszka wrote: > #### Vendor Specific Capability (ID 09h) > > This capability must always be present. > > | Offset | Register | Content | > |-------:|:--------------------|:-----------------------------------------------| > | 00h | ID | 09h | > | 01h | Next Capability | Pointer to next capability or 00h | > | 02h | Length | 20h if Base Address is present, 18h otherwise | > | 03h | Privileged Control | Bit 0 (read/write): one-shot interrupt mode | > | | | Bits 1-7: Reserved (0 on read, writes ignored) | > | 04h | State Table Size | 32-bit size of read-only State Table | > | 08h | R/W Section Size | 64-bit size of common read/write section | > | 10h | Output Section Size | 64-bit size of output sections | > | 18h | Base Address | optional: 64-bit base address of shared memory | > > All registers are read-only. Writes are ignored, except to bit 0 of > the Privileged Control register. Is there value in making this follow the virtio vendor-specific capability format? That will cost several extra bytes - do you envision having many of these in the config space? Also, do we want to define an extended capability format in case this is a pci extended capability? -- MST