From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 7/7] target/arm: Improve IMPDEF algorithm for IRG
Date: Mon, 27 Jul 2020 16:19:20 +0100 [thread overview]
Message-ID: <20200727151920.19150-8-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200727151920.19150-1-peter.maydell@linaro.org>
From: Richard Henderson <richard.henderson@linaro.org>
When GCR_EL1.RRND==1, the choosing of the random value is IMPDEF,
and the kernel is not expected to have set RGSR_EL1. Force a
non-zero value into SEED, so that we do not continually return
the same tag.
Reported-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200724163853.504655-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/mte_helper.c | 37 ++++++++++++++++++++++++++++++-------
1 file changed, 30 insertions(+), 7 deletions(-)
diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c
index 5ea57d487a4..104752041f7 100644
--- a/target/arm/mte_helper.c
+++ b/target/arm/mte_helper.c
@@ -24,6 +24,8 @@
#include "exec/ram_addr.h"
#include "exec/cpu_ldst.h"
#include "exec/helper-proto.h"
+#include "qapi/error.h"
+#include "qemu/guest-random.h"
static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude)
@@ -211,16 +213,37 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, int ptr_mmu_idx,
uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm)
{
- int rtag;
-
- /*
- * Our IMPDEF choice for GCR_EL1.RRND==1 is to behave as if
- * GCR_EL1.RRND==0, always producing deterministic results.
- */
uint16_t exclude = extract32(rm | env->cp15.gcr_el1, 0, 16);
+ int rrnd = extract32(env->cp15.gcr_el1, 16, 1);
int start = extract32(env->cp15.rgsr_el1, 0, 4);
int seed = extract32(env->cp15.rgsr_el1, 8, 16);
- int offset, i;
+ int offset, i, rtag;
+
+ /*
+ * Our IMPDEF choice for GCR_EL1.RRND==1 is to continue to use the
+ * deterministic algorithm. Except that with RRND==1 the kernel is
+ * not required to have set RGSR_EL1.SEED != 0, which is required for
+ * the deterministic algorithm to function. So we force a non-zero
+ * SEED for that case.
+ */
+ if (unlikely(seed == 0) && rrnd) {
+ do {
+ Error *err = NULL;
+ uint16_t two;
+
+ if (qemu_guest_getrandom(&two, sizeof(two), &err) < 0) {
+ /*
+ * Failed, for unknown reasons in the crypto subsystem.
+ * Best we can do is log the reason and use a constant seed.
+ */
+ qemu_log_mask(LOG_UNIMP, "IRG: Crypto failure: %s\n",
+ error_get_pretty(err));
+ error_free(err);
+ two = 1;
+ }
+ seed = two;
+ } while (seed == 0);
+ }
/* RandomTag */
for (i = offset = 0; i < 4; ++i) {
--
2.20.1
next prev parent reply other threads:[~2020-07-27 15:22 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-27 15:19 [PULL 0/7] target-arm queue Peter Maydell
2020-07-27 15:19 ` [PULL 1/7] ACPI: Assert that we don't run out of the preallocated memory Peter Maydell
2020-07-27 15:19 ` [PULL 2/7] hw/misc/aspeed_sdmc: Fix incorrect memory size Peter Maydell
2020-07-27 15:19 ` [PULL 3/7] target/arm: Always pass cacheattr in S1_ptw_translate Peter Maydell
2020-07-27 15:19 ` [PULL 4/7] docs/system/arm/virt: Document 'mte' machine option Peter Maydell
2020-07-27 15:19 ` [PULL 5/7] hw/arm/boot: Fix PAUTH for EL3 direct kernel boot Peter Maydell
2020-07-27 15:19 ` [PULL 6/7] hw/arm/boot: Fix MTE " Peter Maydell
2020-07-27 15:19 ` Peter Maydell [this message]
2020-07-28 18:43 ` [PULL 0/7] target-arm queue Peter Maydell
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