From: Anup Patel <anup.patel@wdc.com>
To: Peter Maydell <peter.maydell@linaro.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Alistair Francis <Alistair.Francis@wdc.com>,
Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Atish Patra <atish.patra@wdc.com>,
Anup Patel <anup.patel@wdc.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org,
Anup Patel <anup@brainfault.org>
Subject: [PATCH 2/3] target/riscv: Fix write_htinst() implementation
Date: Wed, 29 Jul 2020 16:58:00 +0530 [thread overview]
Message-ID: <20200729112801.108985-3-anup.patel@wdc.com> (raw)
In-Reply-To: <20200729112801.108985-1-anup.patel@wdc.com>
The htinst CSR is writeable from M-mode and HS-mode so
we should not ignore writes to htinst CSR.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
---
target/riscv/csr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f985b85de4..99fcb7f67d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -943,6 +943,7 @@ static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
{
+ env->htinst = val;
return 0;
}
--
2.25.1
next prev parent reply other threads:[~2020-07-29 11:31 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-07-29 11:27 [PATCH 0/3] Trapped instruction encoding support Anup Patel
2020-07-29 11:27 ` [PATCH 1/3] target/riscv: Optional feature to provide trapped instruction in CSRs Anup Patel
2020-08-12 22:37 ` Alistair Francis
2020-07-29 11:28 ` Anup Patel [this message]
2020-08-10 22:37 ` [PATCH 2/3] target/riscv: Fix write_htinst() implementation Alistair Francis
2020-07-29 11:28 ` [PATCH 3/3] target/riscv: Update MTINST/HTINST CSR in riscv_cpu_do_interrupt() Anup Patel
2020-08-12 23:16 ` Alistair Francis
2020-08-13 15:52 ` Richard Henderson
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