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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g3sm28013170wrb.59.2020.08.03.04.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2020 04:18:51 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 0/7] target/arm: copro decode cleanup Date: Mon, 3 Aug 2020 12:18:42 +0100 Message-Id: <20200803111849.13368-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This patchset cleans up the handling of copro instructions in the A32/T32 decoder, converting the MRC/MCR/MRRC/MCRR insns to decodetree. The main motivation here was correcting how we do NOCP checks for M-profile: the architecture specifies that the NOCP exception when a coprocessor is not present or disabled should cover the entire wide range of coprocessor-space encodings, and should take precedence over UNDEF exceptions. (This is the opposite of A-profile, where checking for a disabled FPU has to happen last.) This is mandatory from v8.1M and recommended for v8.0M, but we were having UNDEFs in the VFP encodings taking precedence over NOCP. The patchset's solution to this is to have a decodetree decoder which matches (a) the two or three insns which are defined to not get this NOCP behaviour and (b) the area of the encoding space which does need to be NOCP'd if the coprocessor is not present, and invoke this before any of the other decoding. The rest is mostly cleanup: we split out the XScale decode handling from disas_coproc_insn() and then convert the normal coproc insns to decodetree patterns in a32.decode and t32.decode. After these patches, the only remaining "legacy decoder" code is disas_xscale_insn()/disas_iwmmxt_insn(). The conversion does fix a minor underdecoding: we weren't checking that bits [24:21] of MRRC/MCRR were 0b0010, so some patterns that should have been UNDEFed as LDC/STC were instead treated as MRRC/MCRR. It's hard to see it ever being worthwhile to convert the xscale/iwmmxt decode to decodetree -- we don't have the same requirement to be able to add new insn support to it. I suppose we could replace checks like if ((insn & 0x0e000f00) == 0x0c000100) in disas_arm_insn() with a single decodetree pattern in a32.decode that invoked disas_iwmmxt_insn(), but I dunno that that's really any neater... thanks -- PMM Peter Maydell (7): target/arm: Pull handling of XScale insns out of disas_coproc_insn() target/arm: Separate decode from handling of coproc insns target/arm: Convert A32 coprocessor insns to decodetree target/arm: Tidy up disas_arm_insn() target/arm: Do M-profile NOCP checks early and via decodetree target/arm: Convert T32 coprocessor insns to decodetree target/arm: Remove ARCH macro target/arm/a32.decode | 19 +++ target/arm/m-nocp.decode | 42 ++++++ target/arm/t32.decode | 19 +++ target/arm/vfp.decode | 2 - target/arm/helper.c | 29 ++++ target/arm/translate-vfp.inc.c | 52 +++++-- target/arm/translate.c | 240 +++++++++++++++++---------------- target/arm/Makefile.objs | 6 + 8 files changed, 284 insertions(+), 125 deletions(-) create mode 100644 target/arm/m-nocp.decode -- 2.20.1