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Tue, 4 Aug 2020 17:01:14 +0000 (UTC) From: Thomas Huth To: qemu-devel@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [PATCH 02/11] target/riscv/vector_helper: Fix build on 32-bit big endian targets Date: Tue, 4 Aug 2020 19:00:46 +0200 Message-Id: <20200804170055.2851-3-thuth@redhat.com> In-Reply-To: <20200804170055.2851-1-thuth@redhat.com> References: <20200804170055.2851-1-thuth@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=207.211.31.81; envelope-from=thuth@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/08/04 01:01:15 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-1, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=-0.01, RCVD_IN_MSPIKE_WL=-0.01, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Stefan Weil , Wainer dos Santos Moschetta , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" The code currently fails to compile on 32-bit big endian targets: target/riscv/vector_helper.c: In function 'vext_clear': target/riscv/vector_helper.c:154:16: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1); ^ target/riscv/vector_helper.c:155:16: error: cast to pointer from integer of different size [-Werror=int-to-pointer-cast] memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2); ^ cc1: all warnings being treated as errors We should not use "long long" (i.e. 64-bit) values here to avoid the problem. Switch to our QEMU_ALIGN_PTR_DOWN/UP macros instead. Fixes: 751538d5da ("add vector stride load and store instructions") Suggested-by: Philippe Mathieu-Daudé Signed-off-by: Thomas Huth --- target/riscv/vector_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 39f44d1029..793af99067 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -151,8 +151,8 @@ static void vext_clear(void *tail, uint32_t cnt, uint32_t tot) if (cnt % 8) { part1 = 8 - (cnt % 8); part2 = tot - cnt - part1; - memset((void *)((uintptr_t)tail & ~(7ULL)), 0, part1); - memset((void *)(((uintptr_t)tail + 8) & ~(7ULL)), 0, part2); + memset(QEMU_ALIGN_PTR_DOWN(tail, 8), 0, part1); + memset(QEMU_ALIGN_PTR_UP(tail, 8), 0, part2); } else { memset(tail, 0, part2); } -- 2.18.1