From: Eduardo Habkost <ehabkost@redhat.com>
To: qemu-devel@nongnu.org
Cc: "Daniel P. Berrange" <berrange@redhat.com>,
qemu-riscv@nongnu.org,
Sagar Karandikar <sagark@eecs.berkeley.edu>,
Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
Alistair Francis <Alistair.Francis@wdc.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Subject: [PATCH v2 09/58] sifive_u: Rename memmap enum constants
Date: Wed, 19 Aug 2020 20:11:47 -0400 [thread overview]
Message-ID: <20200820001236.1284548-10-ehabkost@redhat.com> (raw)
In-Reply-To: <20200820001236.1284548-1-ehabkost@redhat.com>
Some of the enum constant names conflict with the QOM type check
macros (SIFIVE_U_OTP, SIFIVE_U_PRCI). This needs to be addressed
to allow us to transform the QOM type check macros into functions
generated by OBJECT_DECLARE_TYPE().
Rename all the constants to SIFIVE_U_DEV_*, to avoid conflicts.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
---
Changes v1 -> v2:
* Added more details to commit message
---
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: qemu-riscv@nongnu.org
Cc: qemu-devel@nongnu.org
---
include/hw/riscv/sifive_u.h | 30 ++++----
hw/riscv/sifive_u.c | 136 ++++++++++++++++++------------------
2 files changed, 83 insertions(+), 83 deletions(-)
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index aba4d0181f..0dab922f3a 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -68,21 +68,21 @@ typedef struct SiFiveUState {
} SiFiveUState;
enum {
- SIFIVE_U_DEBUG,
- SIFIVE_U_MROM,
- SIFIVE_U_CLINT,
- SIFIVE_U_L2LIM,
- SIFIVE_U_PLIC,
- SIFIVE_U_PRCI,
- SIFIVE_U_UART0,
- SIFIVE_U_UART1,
- SIFIVE_U_GPIO,
- SIFIVE_U_OTP,
- SIFIVE_U_DMC,
- SIFIVE_U_FLASH0,
- SIFIVE_U_DRAM,
- SIFIVE_U_GEM,
- SIFIVE_U_GEM_MGMT
+ SIFIVE_U_DEV_DEBUG,
+ SIFIVE_U_DEV_MROM,
+ SIFIVE_U_DEV_CLINT,
+ SIFIVE_U_DEV_L2LIM,
+ SIFIVE_U_DEV_PLIC,
+ SIFIVE_U_DEV_PRCI,
+ SIFIVE_U_DEV_UART0,
+ SIFIVE_U_DEV_UART1,
+ SIFIVE_U_DEV_GPIO,
+ SIFIVE_U_DEV_OTP,
+ SIFIVE_U_DEV_DMC,
+ SIFIVE_U_DEV_FLASH0,
+ SIFIVE_U_DEV_DRAM,
+ SIFIVE_U_DEV_GEM,
+ SIFIVE_U_DEV_GEM_MGMT
};
enum {
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index e5682c38a9..0dfbcb5160 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -69,21 +69,21 @@ static const struct MemmapEntry {
hwaddr base;
hwaddr size;
} sifive_u_memmap[] = {
- [SIFIVE_U_DEBUG] = { 0x0, 0x100 },
- [SIFIVE_U_MROM] = { 0x1000, 0xf000 },
- [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 },
- [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 },
- [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 },
- [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 },
- [SIFIVE_U_UART0] = { 0x10010000, 0x1000 },
- [SIFIVE_U_UART1] = { 0x10011000, 0x1000 },
- [SIFIVE_U_GPIO] = { 0x10060000, 0x1000 },
- [SIFIVE_U_OTP] = { 0x10070000, 0x1000 },
- [SIFIVE_U_GEM] = { 0x10090000, 0x2000 },
- [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 },
- [SIFIVE_U_DMC] = { 0x100b0000, 0x10000 },
- [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 },
- [SIFIVE_U_DRAM] = { 0x80000000, 0x0 },
+ [SIFIVE_U_DEV_DEBUG] = { 0x0, 0x100 },
+ [SIFIVE_U_DEV_MROM] = { 0x1000, 0xf000 },
+ [SIFIVE_U_DEV_CLINT] = { 0x2000000, 0x10000 },
+ [SIFIVE_U_DEV_L2LIM] = { 0x8000000, 0x2000000 },
+ [SIFIVE_U_DEV_PLIC] = { 0xc000000, 0x4000000 },
+ [SIFIVE_U_DEV_PRCI] = { 0x10000000, 0x1000 },
+ [SIFIVE_U_DEV_UART0] = { 0x10010000, 0x1000 },
+ [SIFIVE_U_DEV_UART1] = { 0x10011000, 0x1000 },
+ [SIFIVE_U_DEV_GPIO] = { 0x10060000, 0x1000 },
+ [SIFIVE_U_DEV_OTP] = { 0x10070000, 0x1000 },
+ [SIFIVE_U_DEV_GEM] = { 0x10090000, 0x2000 },
+ [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000, 0x1000 },
+ [SIFIVE_U_DEV_DMC] = { 0x100b0000, 0x10000 },
+ [SIFIVE_U_DEV_FLASH0] = { 0x20000000, 0x10000000 },
+ [SIFIVE_U_DEV_DRAM] = { 0x80000000, 0x0 },
};
#define OTP_SERIAL 1
@@ -142,10 +142,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
nodename = g_strdup_printf("/memory@%lx",
- (long)memmap[SIFIVE_U_DRAM].base);
+ (long)memmap[SIFIVE_U_DEV_DRAM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
+ memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
mem_size >> 32, mem_size);
qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
g_free(nodename);
@@ -200,39 +200,39 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
nodename = g_strdup_printf("/soc/clint@%lx",
- (long)memmap[SIFIVE_U_CLINT].base);
+ (long)memmap[SIFIVE_U_DEV_CLINT].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_CLINT].base,
- 0x0, memmap[SIFIVE_U_CLINT].size);
+ 0x0, memmap[SIFIVE_U_DEV_CLINT].base,
+ 0x0, memmap[SIFIVE_U_DEV_CLINT].size);
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
cells, ms->smp.cpus * sizeof(uint32_t) * 4);
g_free(cells);
g_free(nodename);
nodename = g_strdup_printf("/soc/otp@%lx",
- (long)memmap[SIFIVE_U_OTP].base);
+ (long)memmap[SIFIVE_U_DEV_OTP].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_OTP].base,
- 0x0, memmap[SIFIVE_U_OTP].size);
+ 0x0, memmap[SIFIVE_U_DEV_OTP].base,
+ 0x0, memmap[SIFIVE_U_DEV_OTP].size);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-otp");
g_free(nodename);
prci_phandle = phandle++;
nodename = g_strdup_printf("/soc/clock-controller@%lx",
- (long)memmap[SIFIVE_U_PRCI].base);
+ (long)memmap[SIFIVE_U_DEV_PRCI].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
hfclk_phandle, rtcclk_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_PRCI].base,
- 0x0, memmap[SIFIVE_U_PRCI].size);
+ 0x0, memmap[SIFIVE_U_DEV_PRCI].base,
+ 0x0, memmap[SIFIVE_U_DEV_PRCI].size);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-prci");
g_free(nodename);
@@ -256,7 +256,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
}
nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
- (long)memmap[SIFIVE_U_PLIC].base);
+ (long)memmap[SIFIVE_U_DEV_PLIC].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");
@@ -264,8 +264,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_PLIC].base,
- 0x0, memmap[SIFIVE_U_PLIC].size);
+ 0x0, memmap[SIFIVE_U_DEV_PLIC].base,
+ 0x0, memmap[SIFIVE_U_DEV_PLIC].size);
qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
plic_phandle = qemu_fdt_get_phandle(fdt, nodename);
@@ -274,7 +274,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
gpio_phandle = phandle++;
nodename = g_strdup_printf("/soc/gpio@%lx",
- (long)memmap[SIFIVE_U_GPIO].base);
+ (long)memmap[SIFIVE_U_DEV_GPIO].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
@@ -284,8 +284,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_GPIO].base,
- 0x0, memmap[SIFIVE_U_GPIO].size);
+ 0x0, memmap[SIFIVE_U_DEV_GPIO].base,
+ 0x0, memmap[SIFIVE_U_DEV_GPIO].size);
qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,
@@ -304,15 +304,15 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
phy_phandle = phandle++;
nodename = g_strdup_printf("/soc/ethernet@%lx",
- (long)memmap[SIFIVE_U_GEM].base);
+ (long)memmap[SIFIVE_U_DEV_GEM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible",
"sifive,fu540-c000-gem");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_GEM].base,
- 0x0, memmap[SIFIVE_U_GEM].size,
- 0x0, memmap[SIFIVE_U_GEM_MGMT].base,
- 0x0, memmap[SIFIVE_U_GEM_MGMT].size);
+ 0x0, memmap[SIFIVE_U_DEV_GEM].base,
+ 0x0, memmap[SIFIVE_U_DEV_GEM].size,
+ 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
+ 0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);
@@ -333,19 +333,19 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
g_free(nodename);
nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
- (long)memmap[SIFIVE_U_GEM].base);
+ (long)memmap[SIFIVE_U_DEV_GEM].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
g_free(nodename);
nodename = g_strdup_printf("/soc/serial@%lx",
- (long)memmap[SIFIVE_U_UART0].base);
+ (long)memmap[SIFIVE_U_DEV_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
qemu_fdt_setprop_cells(fdt, nodename, "reg",
- 0x0, memmap[SIFIVE_U_UART0].base,
- 0x0, memmap[SIFIVE_U_UART0].size);
+ 0x0, memmap[SIFIVE_U_DEV_UART0].base,
+ 0x0, memmap[SIFIVE_U_DEV_UART0].size);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
prci_phandle, PRCI_CLK_TLCLK);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
@@ -377,7 +377,7 @@ static void sifive_u_machine_init(MachineState *machine)
MemoryRegion *system_memory = get_system_memory();
MemoryRegion *main_mem = g_new(MemoryRegion, 1);
MemoryRegion *flash0 = g_new(MemoryRegion, 1);
- target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
+ target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
uint32_t start_addr_hi32 = 0x00000000;
int i;
uint32_t fdt_load_addr;
@@ -392,13 +392,13 @@ static void sifive_u_machine_init(MachineState *machine)
/* register RAM */
memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
machine->ram_size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
main_mem);
/* register QSPI0 Flash */
memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
- memmap[SIFIVE_U_FLASH0].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
+ memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
flash0);
/* register gpio-restart */
@@ -424,14 +424,14 @@ static void sifive_u_machine_init(MachineState *machine)
switch (s->msel) {
case MSEL_MEMMAP_QSPI0_FLASH:
- start_addr = memmap[SIFIVE_U_FLASH0].base;
+ start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
break;
case MSEL_L2LIM_QSPI0_FLASH:
case MSEL_L2LIM_QSPI2_SD:
- start_addr = memmap[SIFIVE_U_L2LIM].base;
+ start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
break;
default:
- start_addr = memmap[SIFIVE_U_DRAM].base;
+ start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
break;
}
@@ -459,7 +459,7 @@ static void sifive_u_machine_init(MachineState *machine)
}
/* Compute the fdt load address in dram */
- fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
+ fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
machine->ram_size, s->fdt);
#if defined(TARGET_RISCV64)
start_addr_hi32 = start_addr >> 32;
@@ -491,10 +491,10 @@ static void sifive_u_machine_init(MachineState *machine)
reset_vec[i] = cpu_to_le32(reset_vec[i]);
}
rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
- memmap[SIFIVE_U_MROM].base, &address_space_memory);
+ memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
- riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base,
- memmap[SIFIVE_U_MROM].size,
+ riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base,
+ memmap[SIFIVE_U_DEV_MROM].size,
sizeof(reset_vec), kernel_entry);
}
@@ -634,8 +634,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
/* boot rom */
memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
- memmap[SIFIVE_U_MROM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
+ memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
mask_rom);
/*
@@ -648,8 +648,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
* too generous to misbehaving guests.
*/
memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
- memmap[SIFIVE_U_L2LIM].size, &error_fatal);
- memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
+ memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
+ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
l2lim_mem);
/* create PLIC hart topology configuration string */
@@ -667,7 +667,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
}
/* MMIO */
- s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
+ s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
plic_hart_config,
SIFIVE_U_PLIC_NUM_SOURCES,
SIFIVE_U_PLIC_NUM_PRIORITIES,
@@ -677,26 +677,26 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_U_PLIC_ENABLE_STRIDE,
SIFIVE_U_PLIC_CONTEXT_BASE,
SIFIVE_U_PLIC_CONTEXT_STRIDE,
- memmap[SIFIVE_U_PLIC].size);
+ memmap[SIFIVE_U_DEV_PLIC].size);
g_free(plic_hart_config);
- sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
+ sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
- sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
+ sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
- sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
- memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
+ sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
+ memmap[SIFIVE_U_DEV_CLINT].size, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
/* Pass all GPIOs to the SOC layer so they are available to the board */
qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);
@@ -712,7 +712,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
/* FIXME use qdev NIC properties instead of nd_table[] */
if (nd->used) {
@@ -724,15 +724,15 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
return;
}
- sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
create_unimplemented_device("riscv.sifive.u.gem-mgmt",
- memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
+ memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
create_unimplemented_device("riscv.sifive.u.dmc",
- memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
+ memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
}
static Property sifive_u_soc_props[] = {
--
2.26.2
next prev parent reply other threads:[~2020-08-20 0:14 UTC|newest]
Thread overview: 112+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-20 0:11 [PATCH v2 00/58] qom: Automated conversion of type checking boilerplate Eduardo Habkost
2020-08-20 0:11 ` [PATCH v2 01/58] e1000: Rename QOM class cast macros Eduardo Habkost
2020-08-20 0:11 ` [PATCH v2 02/58] megasas: " Eduardo Habkost
2020-08-20 0:11 ` [PATCH v2 03/58] vmw_pvscsi: " Eduardo Habkost
2020-08-20 0:11 ` [PATCH v2 04/58] pl110: Rename pl110_version enum values Eduardo Habkost
2020-08-20 13:11 ` Philippe Mathieu-Daudé
2020-08-25 11:05 ` Daniel P. Berrangé
2020-08-20 0:11 ` [PATCH v2 05/58] allwinner-h3: Rename memmap enum constants Eduardo Habkost
2020-08-21 19:42 ` Niek Linnenbank
2020-08-25 11:07 ` Daniel P. Berrangé
2020-08-20 0:11 ` [PATCH v2 06/58] aspeed_soc: Rename memmap/irqmap " Eduardo Habkost
2020-08-20 6:41 ` Cédric Le Goater
2020-08-25 11:08 ` Daniel P. Berrangé
2020-08-20 0:11 ` [PATCH v2 07/58] opentitan: Rename memmap " Eduardo Habkost
2020-08-25 11:09 ` Daniel P. Berrangé
2020-08-20 0:11 ` [PATCH v2 08/58] sifive_e: " Eduardo Habkost
2020-08-25 11:10 ` Daniel P. Berrangé
2020-08-20 0:11 ` Eduardo Habkost [this message]
2020-08-25 11:10 ` [PATCH v2 09/58] sifive_u: " Daniel P. Berrangé
2020-08-20 0:11 ` [PATCH v2 10/58] aspeed_timer: Fix ASPEED_TIMER macro definition Eduardo Habkost
2020-08-20 6:42 ` Cédric Le Goater
2020-08-20 0:11 ` [PATCH v2 11/58] versatile: Fix typo in PCI_VPB_HOST definition Eduardo Habkost
2020-08-20 0:11 ` [PATCH v2 12/58] virtio-ccw: Fix definition of VIRTIO_CCW_BUS_GET_CLASS Eduardo Habkost
2020-08-21 18:19 ` David Hildenbrand
2020-08-20 0:11 ` [PATCH v2 13/58] hvf: Add missing include Eduardo Habkost
2020-08-20 0:11 ` [PATCH v2 14/58] hcd-dwc2: Rename USB_*CLASS macros for consistency Eduardo Habkost
2020-08-20 0:11 ` [PATCH v2 15/58] tulip: Move TulipState typedef to header Eduardo Habkost
2020-08-20 0:11 ` [PATCH v2 16/58] throttle-groups: Move ThrottleGroup " Eduardo Habkost
2020-08-20 0:11 ` [PATCH v2 17/58] pci: Move PCIBusClass typedef to pci.h Eduardo Habkost
2020-08-20 0:11 ` [PATCH v2 18/58] i8254: Move PITCommonState/PITCommonClass typedefs to i8254.h Eduardo Habkost
2020-08-20 0:11 ` [PATCH v2 19/58] hvf: Move HVFState typedef to hvf.h Eduardo Habkost
2020-08-21 11:17 ` Roman Bolshakov
2020-08-21 11:23 ` Roman Bolshakov
2020-08-25 11:35 ` Eduardo Habkost
2020-08-20 0:11 ` [PATCH v2 20/58] mcf_fec: Move mcf_fec_state typedef to header Eduardo Habkost
2020-08-27 8:09 ` Thomas Huth
2020-08-20 0:11 ` [PATCH v2 21/58] s390_flic: Move KVMS390FLICState " Eduardo Habkost
2020-08-20 0:12 ` [PATCH v2 22/58] can_emu: Delete macros for non-existing typedef Eduardo Habkost
2020-08-20 0:12 ` [PATCH v2 23/58] nubus: Delete unused NUBUS_BRIDGE macro Eduardo Habkost
2020-08-20 15:05 ` Laurent Vivier
2020-08-20 0:12 ` [PATCH v2 24/58] platform-bus: Delete macros for non-existing typedef Eduardo Habkost
2020-08-20 0:12 ` [PATCH v2 25/58] armsse: Rename QOM macros to avoid conflicts Eduardo Habkost
2020-08-25 11:12 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 26/58] xen-legacy-backend: Add missing typedef XenLegacyDevice Eduardo Habkost
2020-08-20 15:34 ` Anthony PERARD via
2020-08-25 11:12 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 27/58] spapr: Move typedef SpaprMachineState to spapr.h Eduardo Habkost
2020-08-25 11:13 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 28/58] s390x: Move typedef SCLPEventFacility to event-facility.h Eduardo Habkost
2020-08-20 7:03 ` Cornelia Huck
2020-08-25 11:13 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 29/58] vhost-user-gpu: Move QOM macro to header Eduardo Habkost
2020-08-20 5:39 ` Gerd Hoffmann
2020-08-25 11:15 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 30/58] ahci: Move QOM macros " Eduardo Habkost
2020-08-25 11:15 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 31/58] i8257: Move QOM macro " Eduardo Habkost
2020-08-25 11:16 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 32/58] ahci: " Eduardo Habkost
2020-08-25 11:16 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 33/58] pckbd: " Eduardo Habkost
2020-08-25 11:16 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 34/58] vmbus: Move QOM macros to vmbus.h Eduardo Habkost
2020-08-25 11:17 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 35/58] virtio-serial-bus: Move QOM macros to header Eduardo Habkost
2020-08-25 11:17 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 36/58] piix: " Eduardo Habkost
2020-08-20 13:13 ` Philippe Mathieu-Daudé
2020-08-25 11:18 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 37/58] auxbus: " Eduardo Habkost
2020-08-25 11:18 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 38/58] rocker: " Eduardo Habkost
2020-08-25 11:19 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 39/58] pxa2xx: " Eduardo Habkost
2020-08-25 11:19 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 40/58] mptsas: " Eduardo Habkost
2020-08-25 11:20 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 41/58] kvm: Move QOM macros to kvm.h Eduardo Habkost
2020-08-25 11:20 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 42/58] vfio/pci: Move QOM macros to header Eduardo Habkost
2020-08-20 13:14 ` Philippe Mathieu-Daudé
2020-08-20 13:14 ` Philippe Mathieu-Daudé
2020-08-25 11:20 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 43/58] qom: make object_ref/unref use a void * instead of Object * Eduardo Habkost
2020-08-20 0:12 ` [PATCH v2 44/58] qom: provide convenient macros for declaring and defining types Eduardo Habkost
2020-08-20 17:45 ` Eduardo Habkost
2020-08-20 17:57 ` Daniel P. Berrangé
2020-08-20 18:48 ` Eduardo Habkost
2020-08-20 18:40 ` Laurent Vivier
2020-08-20 0:12 ` [PATCH v2 45/58] qom: Allow class type name to be specified in OBJECT_DECLARE* Eduardo Habkost
2020-08-20 0:12 ` [PATCH v2 46/58] qom: DECLARE_*_CHECKERS macros Eduardo Habkost
2020-08-20 0:12 ` [PATCH v2 47/58] qom: Make type checker functions accept const pointers Eduardo Habkost
2020-08-20 0:12 ` [PATCH v2 48/58] qom: TYPE_INFO macro Eduardo Habkost
2020-08-20 0:12 ` [PATCH v2 49/58] codeconverter: script for automating QOM code cleanups Eduardo Habkost
2020-08-20 0:12 ` [PATCH v2 50/58] [automated] Delete duplicate QOM typedefs Eduardo Habkost
2020-08-20 0:12 ` [PATCH v2 51/58] [automated] Use TYPE_INFO macro Eduardo Habkost
2020-08-20 0:12 ` [PATCH v2 52/58] [automated] Move QOM typedefs and add missing includes Eduardo Habkost
2020-08-25 11:26 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 53/58] [automated] Use DECLARE_*CHECKER* macros Eduardo Habkost
2020-08-25 11:35 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 54/58] [semi-automated] Use DECLARE_*CHECKER* when possible (--force mode) Eduardo Habkost
2020-08-25 11:43 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 55/58] [automated] Use OBJECT_DECLARE_TYPE where possible Eduardo Habkost
2020-08-25 11:47 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 56/58] [automated] Use OBJECT_DECLARE_SIMPLE_TYPE when possible Eduardo Habkost
2020-08-25 11:49 ` Daniel P. Berrangé
2020-08-20 0:12 ` [PATCH v2 57/58] crypto: use QOM macros for declaration/definition of secret types Eduardo Habkost
2020-08-20 0:12 ` [PATCH v2 58/58] crypto: use QOM macros for declaration/definition of TLS creds types Eduardo Habkost
2020-08-20 0:18 ` [PATCH v2 00/58] qom: Automated conversion of type checking boilerplate Eduardo Habkost
2020-08-20 0:55 ` no-reply
2020-08-20 1:00 ` no-reply
2020-08-20 1:09 ` no-reply
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200820001236.1284548-10-ehabkost@redhat.com \
--to=ehabkost@redhat.com \
--cc=Alistair.Francis@wdc.com \
--cc=berrange@redhat.com \
--cc=kbastian@mail.uni-paderborn.de \
--cc=palmer@dabbelt.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=sagark@eecs.berkeley.edu \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).