From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 12/27] hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation
Date: Mon, 24 Aug 2020 10:47:56 +0100 [thread overview]
Message-ID: <20200824094811.15439-13-peter.maydell@linaro.org> (raw)
In-Reply-To: <20200824094811.15439-1-peter.maydell@linaro.org>
From: Eric Auger <eric.auger@redhat.com>
Expose the RIL bit so that the guest driver uses range
invalidation. Although RIL is a 3.2 features, We let
the AIDR advertise SMMUv3.1 support as v3.x implementation
is allowed to implement features from v3.(x+1).
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-12-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/smmuv3-internal.h | 1 +
hw/arm/smmuv3.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/hw/arm/smmuv3-internal.h b/hw/arm/smmuv3-internal.h
index 9ae7d97fafd..fa3c088972e 100644
--- a/hw/arm/smmuv3-internal.h
+++ b/hw/arm/smmuv3-internal.h
@@ -55,6 +55,7 @@ REG32(IDR1, 0x4)
REG32(IDR2, 0x8)
REG32(IDR3, 0xc)
FIELD(IDR3, HAD, 2, 1);
+ FIELD(IDR3, RIL, 10, 1);
REG32(IDR4, 0x10)
REG32(IDR5, 0x14)
FIELD(IDR5, OAS, 0, 3);
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index b262f0e4a74..0122700e725 100644
--- a/hw/arm/smmuv3.c
+++ b/hw/arm/smmuv3.c
@@ -254,6 +254,7 @@ static void smmuv3_init_regs(SMMUv3State *s)
s->idr[1] = FIELD_DP32(s->idr[1], IDR1, EVENTQS, SMMU_EVENTQS);
s->idr[1] = FIELD_DP32(s->idr[1], IDR1, CMDQS, SMMU_CMDQS);
+ s->idr[3] = FIELD_DP32(s->idr[3], IDR3, RIL, 1);
s->idr[3] = FIELD_DP32(s->idr[3], IDR3, HAD, 1);
/* 4K and 64K granule support */
--
2.20.1
next prev parent reply other threads:[~2020-08-24 9:53 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-24 9:47 [PULL 00/27] target-arm queue Peter Maydell
2020-08-24 9:47 ` [PULL 01/27] hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores Peter Maydell
2020-08-24 9:47 ` [PULL 02/27] hw/arm/smmu-common: Factorize some code in smmu_ptw_64() Peter Maydell
2020-08-24 9:47 ` [PULL 03/27] hw/arm/smmu-common: Add IOTLB helpers Peter Maydell
2020-08-24 9:47 ` [PULL 04/27] hw/arm/smmu: Introduce smmu_get_iotlb_key() Peter Maydell
2020-08-24 9:47 ` [PULL 05/27] hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value Peter Maydell
2020-08-24 9:47 ` [PULL 06/27] hw/arm/smmu-common: Manage IOTLB block entries Peter Maydell
2020-08-24 9:47 ` [PULL 07/27] hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper Peter Maydell
2020-08-24 9:47 ` [PULL 08/27] hw/arm/smmuv3: Get prepared for range invalidation Peter Maydell
2020-08-24 9:47 ` [PULL 09/27] hw/arm/smmuv3: Fix IIDR offset Peter Maydell
2020-08-24 9:47 ` [PULL 10/27] hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support Peter Maydell
2020-08-24 9:47 ` [PULL 11/27] hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support Peter Maydell
2020-08-24 9:47 ` Peter Maydell [this message]
2020-08-24 9:47 ` [PULL 13/27] docs/system/arm: Document the Xilinx Versal Virt board Peter Maydell
2020-08-24 9:47 ` [PULL 14/27] target/arm: Pull handling of XScale insns out of disas_coproc_insn() Peter Maydell
2020-08-24 9:47 ` [PULL 15/27] target/arm: Separate decode from handling of coproc insns Peter Maydell
2020-08-24 9:48 ` [PULL 16/27] target/arm: Convert A32 coprocessor insns to decodetree Peter Maydell
2020-08-24 9:48 ` [PULL 17/27] target/arm: Tidy up disas_arm_insn() Peter Maydell
2020-08-24 9:48 ` [PULL 18/27] target/arm: Do M-profile NOCP checks early and via decodetree Peter Maydell
2020-08-24 9:48 ` [PULL 19/27] target/arm: Convert T32 coprocessor insns to decodetree Peter Maydell
2020-08-24 9:48 ` [PULL 20/27] target/arm: Remove ARCH macro Peter Maydell
2020-08-24 9:48 ` [PULL 21/27] target/arm: Delete unused VFP_DREG macros Peter Maydell
2020-08-24 9:48 ` [PULL 22/27] target/arm/translate.c: Delete/amend incorrect comments Peter Maydell
2020-08-24 9:48 ` [PULL 23/27] target/arm: Delete unused ARM_FEATURE_CRC Peter Maydell
2020-08-24 9:48 ` [PULL 24/27] target/arm: Replace A64 get_fpstatus_ptr() with generic fpstatus_ptr() Peter Maydell
2020-08-24 9:48 ` [PULL 25/27] target/arm: Make A32/T32 use new fpstatus_ptr() API Peter Maydell
2020-08-24 9:48 ` [PULL 26/27] target/arm: Implement FPST_STD_F16 fpstatus Peter Maydell
2020-08-24 9:48 ` [PULL 27/27] target/arm: Use correct FPST for VCMLA, VCADD on fp16 Peter Maydell
2020-08-24 13:53 ` [PULL 00/27] target-arm queue Peter Maydell
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20200824094811.15439-13-peter.maydell@linaro.org \
--to=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).