* [PULL v1 1/8] target/microblaze: mbar: Transfer dc->rd to mbar_imm
2020-08-24 10:00 [PULL v1 0/8] Xilinx queue 2020-08-14 Edgar E. Iglesias
@ 2020-08-24 10:00 ` Edgar E. Iglesias
2020-08-24 10:00 ` [PULL v1 2/8] target/microblaze: mbar: Move LOG_DIS to before sleep Edgar E. Iglesias
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Edgar E. Iglesias @ 2020-08-24 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: edgar.iglesias, peter.maydell
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Transfer dc->rd to mbar_imm to improve the readability when
comparing to the specs.
No functional change.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/translate.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index f6ff2591c3..47637f152b 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1229,8 +1229,10 @@ static void dec_br(DisasContext *dc)
/* Memory barrier. */
mbar = (dc->ir >> 16) & 31;
if (mbar == 2 && dc->imm == 4) {
+ uint16_t mbar_imm = dc->rd;
+
/* mbar IMM & 16 decodes to sleep. */
- if (dc->rd & 16) {
+ if (mbar_imm & 16) {
TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT);
TCGv_i32 tmp_1 = tcg_const_i32(1);
@@ -1246,7 +1248,7 @@ static void dec_br(DisasContext *dc)
tcg_temp_free_i32(tmp_1);
return;
}
- LOG_DIS("mbar %d\n", dc->rd);
+ LOG_DIS("mbar %d\n", mbar_imm);
/* Break the TB. */
dc->cpustate_changed = 1;
return;
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PULL v1 2/8] target/microblaze: mbar: Move LOG_DIS to before sleep
2020-08-24 10:00 [PULL v1 0/8] Xilinx queue 2020-08-14 Edgar E. Iglesias
2020-08-24 10:00 ` [PULL v1 1/8] target/microblaze: mbar: Transfer dc->rd to mbar_imm Edgar E. Iglesias
@ 2020-08-24 10:00 ` Edgar E. Iglesias
2020-08-24 10:00 ` [PULL v1 3/8] target/microblaze: mbar: Add support for data-access barriers Edgar E. Iglesias
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Edgar E. Iglesias @ 2020-08-24 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: edgar.iglesias, peter.maydell
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Move LOG_DIS log to before sleeping handling so that it logs
for sleep instructions aswell.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/translate.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 47637f152b..c1be76d4c8 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1231,6 +1231,8 @@ static void dec_br(DisasContext *dc)
if (mbar == 2 && dc->imm == 4) {
uint16_t mbar_imm = dc->rd;
+ LOG_DIS("mbar %d\n", mbar_imm);
+
/* mbar IMM & 16 decodes to sleep. */
if (mbar_imm & 16) {
TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT);
@@ -1248,7 +1250,6 @@ static void dec_br(DisasContext *dc)
tcg_temp_free_i32(tmp_1);
return;
}
- LOG_DIS("mbar %d\n", mbar_imm);
/* Break the TB. */
dc->cpustate_changed = 1;
return;
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PULL v1 3/8] target/microblaze: mbar: Add support for data-access barriers
2020-08-24 10:00 [PULL v1 0/8] Xilinx queue 2020-08-14 Edgar E. Iglesias
2020-08-24 10:00 ` [PULL v1 1/8] target/microblaze: mbar: Transfer dc->rd to mbar_imm Edgar E. Iglesias
2020-08-24 10:00 ` [PULL v1 2/8] target/microblaze: mbar: Move LOG_DIS to before sleep Edgar E. Iglesias
@ 2020-08-24 10:00 ` Edgar E. Iglesias
2020-08-24 10:00 ` [PULL v1 4/8] target/microblaze: swx: Use atomic_cmpxchg Edgar E. Iglesias
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Edgar E. Iglesias @ 2020-08-24 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: edgar.iglesias, peter.maydell
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add support for data-access barriers.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/translate.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index c1be76d4c8..c58f334a0f 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1233,6 +1233,11 @@ static void dec_br(DisasContext *dc)
LOG_DIS("mbar %d\n", mbar_imm);
+ /* Data access memory barrier. */
+ if ((mbar_imm & 2) == 0) {
+ tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL);
+ }
+
/* mbar IMM & 16 decodes to sleep. */
if (mbar_imm & 16) {
TCGv_i32 tmp_hlt = tcg_const_i32(EXCP_HLT);
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PULL v1 4/8] target/microblaze: swx: Use atomic_cmpxchg
2020-08-24 10:00 [PULL v1 0/8] Xilinx queue 2020-08-14 Edgar E. Iglesias
` (2 preceding siblings ...)
2020-08-24 10:00 ` [PULL v1 3/8] target/microblaze: mbar: Add support for data-access barriers Edgar E. Iglesias
@ 2020-08-24 10:00 ` Edgar E. Iglesias
2020-08-24 10:00 ` [PULL v1 5/8] configure: microblaze: Enable mttcg Edgar E. Iglesias
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Edgar E. Iglesias @ 2020-08-24 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: edgar.iglesias, peter.maydell
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Use atomic_cmpxchg to implement the atomic cmpxchg sequence.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/translate.c | 21 +++++++++++++--------
1 file changed, 13 insertions(+), 8 deletions(-)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index c58f334a0f..530c15e5ad 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1075,14 +1075,16 @@ static void dec_store(DisasContext *dc)
swx_skip = gen_new_label();
tcg_gen_brcond_tl(TCG_COND_NE, env_res_addr, addr, swx_skip);
- /* Compare the value loaded at lwx with current contents of
- the reserved location.
- FIXME: This only works for system emulation where we can expect
- this compare and the following write to be atomic. For user
- emulation we need to add atomicity between threads. */
+ /*
+ * Compare the value loaded at lwx with current contents of
+ * the reserved location.
+ */
tval = tcg_temp_new_i32();
- tcg_gen_qemu_ld_i32(tval, addr, cpu_mmu_index(&dc->cpu->env, false),
- MO_TEUL);
+
+ tcg_gen_atomic_cmpxchg_i32(tval, addr, env_res_val,
+ cpu_R[dc->rd], mem_index,
+ mop);
+
tcg_gen_brcond_i32(TCG_COND_NE, env_res_val, tval, swx_skip);
write_carryi(dc, 0);
tcg_temp_free_i32(tval);
@@ -1108,7 +1110,10 @@ static void dec_store(DisasContext *dc)
break;
}
}
- tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop);
+
+ if (!ex) {
+ tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop);
+ }
/* Verify alignment if needed. */
if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PULL v1 5/8] configure: microblaze: Enable mttcg
2020-08-24 10:00 [PULL v1 0/8] Xilinx queue 2020-08-14 Edgar E. Iglesias
` (3 preceding siblings ...)
2020-08-24 10:00 ` [PULL v1 4/8] target/microblaze: swx: Use atomic_cmpxchg Edgar E. Iglesias
@ 2020-08-24 10:00 ` Edgar E. Iglesias
2020-08-24 10:00 ` [PULL v1 6/8] target/microblaze: mbar: Trap sleeps from user-space Edgar E. Iglesias
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Edgar E. Iglesias @ 2020-08-24 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: edgar.iglesias, peter.maydell
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
configure | 1 +
1 file changed, 1 insertion(+)
diff --git a/configure b/configure
index 67832e3bab..b8f5b81a67 100755
--- a/configure
+++ b/configure
@@ -7782,6 +7782,7 @@ case "$target_name" in
microblaze|microblazeel)
TARGET_ARCH=microblaze
TARGET_SYSTBL_ABI=common
+ mttcg="yes"
bflt="yes"
echo "TARGET_ABI32=y" >> $config_target_mak
;;
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PULL v1 6/8] target/microblaze: mbar: Trap sleeps from user-space
2020-08-24 10:00 [PULL v1 0/8] Xilinx queue 2020-08-14 Edgar E. Iglesias
` (4 preceding siblings ...)
2020-08-24 10:00 ` [PULL v1 5/8] configure: microblaze: Enable mttcg Edgar E. Iglesias
@ 2020-08-24 10:00 ` Edgar E. Iglesias
2020-08-24 10:00 ` [PULL v1 7/8] microblaze: petalogix-ml605: Add device-tree source Edgar E. Iglesias
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Edgar E. Iglesias @ 2020-08-24 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: edgar.iglesias, peter.maydell
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Trap mbar-sleeps from user-space.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
target/microblaze/translate.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 530c15e5ad..a96cb21d96 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1250,6 +1250,11 @@ static void dec_br(DisasContext *dc)
LOG_DIS("sleep\n");
+ if (trap_userspace(dc, true)) {
+ /* Sleep is a privileged instruction. */
+ return;
+ }
+
t_sync_flags(dc);
tcg_gen_st_i32(tmp_1, cpu_env,
-offsetof(MicroBlazeCPU, env)
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PULL v1 7/8] microblaze: petalogix-ml605: Add device-tree source
2020-08-24 10:00 [PULL v1 0/8] Xilinx queue 2020-08-14 Edgar E. Iglesias
` (5 preceding siblings ...)
2020-08-24 10:00 ` [PULL v1 6/8] target/microblaze: mbar: Trap sleeps from user-space Edgar E. Iglesias
@ 2020-08-24 10:00 ` Edgar E. Iglesias
2020-08-24 10:00 ` [PULL v1 8/8] microblaze: petalogix-s3adsp1800: " Edgar E. Iglesias
2020-08-24 15:32 ` [PULL v1 0/8] Xilinx queue 2020-08-14 Peter Maydell
8 siblings, 0 replies; 10+ messages in thread
From: Edgar E. Iglesias @ 2020-08-24 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: edgar.iglesias, peter.maydell
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add a device-tree source for petalogix-ml605 and recompile
the DTB.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
pc-bios/petalogix-ml605.dtb | Bin 9982 -> 9882 bytes
pc-bios/petalogix-ml605.dts | 350 ++++++++++++++++++++++++++++++++++++
2 files changed, 350 insertions(+)
create mode 100644 pc-bios/petalogix-ml605.dts
diff --git a/pc-bios/petalogix-ml605.dtb b/pc-bios/petalogix-ml605.dtb
index fbbd45fdad06489c6333b6de868f44dfaed405bf..9a05434db7f622d1b598d2cf1415c867cf7f5cc6 100644
GIT binary patch
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diff --git a/pc-bios/petalogix-ml605.dts b/pc-bios/petalogix-ml605.dts
new file mode 100644
index 0000000000..b307a29279
--- /dev/null
+++ b/pc-bios/petalogix-ml605.dts
@@ -0,0 +1,350 @@
+/*
+ * Copyright (c) 2020 Xilinx Inc.
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x01 >;
+ compatible = "xlnx,microblaze";
+ model = "edk131";
+
+ memory@50000000 {
+ device_type = "memory";
+ reg = < 0x50000000 0x10000000 >;
+ };
+
+ aliases {
+ ethernet0 = "/axi/axi-ethernet@82780000";
+ serial0 = "/axi/serial@83e00000";
+ };
+
+ chosen {
+ bootargs = " console=ttyS0,115200 ";
+ stdout-path = "/axi/serial@83e00000";
+ };
+
+ cpus {
+ #address-cells = < 0x01 >;
+ #cpus = < 0x01 >;
+ #size-cells = < 0x00 >;
+
+ cpu@0 {
+ clock-frequency = < 0xbebc200 >;
+ compatible = "xlnx,microblaze-8.10.a";
+ d-cache-baseaddr = < 0x50000000 >;
+ d-cache-highaddr = < 0x5fffffff >;
+ d-cache-line-size = < 0x20 >;
+ d-cache-size = < 0x800 >;
+ device_type = "cpu";
+ i-cache-baseaddr = < 0x50000000 >;
+ i-cache-highaddr = < 0x5fffffff >;
+ i-cache-line-size = < 0x20 >;
+ i-cache-size = < 0x800 >;
+ model = "microblaze,8.10.a";
+ reg = < 0x00 >;
+ timebase-frequency = < 0xbebc200 >;
+ xlnx,addr-tag-bits = < 0x11 >;
+ xlnx,allow-dcache-wr = < 0x01 >;
+ xlnx,allow-icache-wr = < 0x01 >;
+ xlnx,area-optimized = < 0x00 >;
+ xlnx,branch-target-cache-size = < 0x00 >;
+ xlnx,cache-byte-size = < 0x800 >;
+ xlnx,d-axi = < 0x01 >;
+ xlnx,d-lmb = < 0x01 >;
+ xlnx,d-plb = < 0x00 >;
+ xlnx,data-size = < 0x20 >;
+ xlnx,dcache-addr-tag = < 0x11 >;
+ xlnx,dcache-always-used = < 0x01 >;
+ xlnx,dcache-byte-size = < 0x800 >;
+ xlnx,dcache-data-width = < 0x00 >;
+ xlnx,dcache-force-tag-lutram = < 0x00 >;
+ xlnx,dcache-interface = < 0x01 >;
+ xlnx,dcache-line-len = < 0x08 >;
+ xlnx,dcache-use-fsl = < 0x00 >;
+ xlnx,dcache-use-writeback = < 0x01 >;
+ xlnx,dcache-victims = < 0x00 >;
+ xlnx,debug-enabled = < 0x01 >;
+ xlnx,div-zero-exception = < 0x01 >;
+ xlnx,dynamic-bus-sizing = < 0x01 >;
+ xlnx,ecc-use-ce-exception = < 0x00 >;
+ xlnx,edge-is-positive = < 0x01 >;
+ xlnx,endianness = < 0x01 >;
+ xlnx,family = "virtex6";
+ xlnx,fault-tolerant = < 0x00 >;
+ xlnx,fpu-exception = < 0x01 >;
+ xlnx,freq = < 0xbebc200 >;
+ xlnx,fsl-data-size = < 0x20 >;
+ xlnx,fsl-exception = < 0x00 >;
+ xlnx,fsl-links = < 0x00 >;
+ xlnx,i-axi = < 0x01 >;
+ xlnx,i-lmb = < 0x01 >;
+ xlnx,i-plb = < 0x00 >;
+ xlnx,icache-always-used = < 0x01 >;
+ xlnx,icache-data-width = < 0x00 >;
+ xlnx,icache-force-tag-lutram = < 0x00 >;
+ xlnx,icache-interface = < 0x00 >;
+ xlnx,icache-line-len = < 0x08 >;
+ xlnx,icache-streams = < 0x00 >;
+ xlnx,icache-use-fsl = < 0x00 >;
+ xlnx,icache-victims = < 0x00 >;
+ xlnx,ill-opcode-exception = < 0x01 >;
+ xlnx,instance = "microblaze_0";
+ xlnx,interconnect = < 0x02 >;
+ xlnx,interrupt-is-edge = < 0x00 >;
+ xlnx,mmu-dtlb-size = < 0x04 >;
+ xlnx,mmu-itlb-size = < 0x02 >;
+ xlnx,mmu-privileged-instr = < 0x00 >;
+ xlnx,mmu-tlb-access = < 0x03 >;
+ xlnx,mmu-zones = < 0x02 >;
+ xlnx,number-of-pc-brk = < 0x01 >;
+ xlnx,number-of-rd-addr-brk = < 0x00 >;
+ xlnx,number-of-wr-addr-brk = < 0x00 >;
+ xlnx,opcode-0x0-illegal = < 0x01 >;
+ xlnx,optimization = < 0x00 >;
+ xlnx,pvr = < 0x02 >;
+ xlnx,pvr-user1 = < 0x00 >;
+ xlnx,pvr-user2 = < 0x00 >;
+ xlnx,reset-msr = < 0x00 >;
+ xlnx,sco = < 0x00 >;
+ xlnx,stream-interconnect = < 0x00 >;
+ xlnx,unaligned-exceptions = < 0x01 >;
+ xlnx,use-barrel = < 0x01 >;
+ xlnx,use-branch-target-cache = < 0x00 >;
+ xlnx,use-dcache = < 0x01 >;
+ xlnx,use-div = < 0x01 >;
+ xlnx,use-ext-brk = < 0x01 >;
+ xlnx,use-ext-nm-brk = < 0x01 >;
+ xlnx,use-extended-fsl-instr = < 0x00 >;
+ xlnx,use-fpu = < 0x01 >;
+ xlnx,use-hw-mul = < 0x02 >;
+ xlnx,use-icache = < 0x01 >;
+ xlnx,use-interrupt = < 0x01 >;
+ xlnx,use-mmu = < 0x03 >;
+ xlnx,use-msr-instr = < 0x01 >;
+ xlnx,use-pcmp-instr = < 0x01 >;
+ xlnx,use-stack-protection = < 0x00 >;
+ };
+ };
+
+ axi {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x01 >;
+ compatible = "xlnx,axi-interconnect-1.02.a\0simple-bus";
+ ranges;
+
+ axi-ethernet@82780000 {
+ axistream-connected = < &axi_dma >;
+ compatible = "xlnx,axi-ethernet-2.01.a\0xlnx,axi-ethernet-1.00.a";
+ device_type = "network";
+ interrupt-parent = < &intc >;
+ interrupts = < 0x03 0x02 >;
+ local-mac-address = [ 00 0a 35 00 22 01 ];
+ phy-handle = < &phy7 >;
+ reg = < 0x82780000 0x40000 >;
+ xlnx,avb = < 0x00 >;
+ xlnx,halfdup = < 0x00 >;
+ xlnx,include-io = < 0x01 >;
+ xlnx,mcast-extend = < 0x00 >;
+ xlnx,phy-type = < 0x01 >;
+ xlnx,phyaddr = "0B00001";
+ xlnx,rxcsum = < 0x00 >;
+ xlnx,rxmem = < 0x1000 >;
+ xlnx,rxvlan-strp = < 0x00 >;
+ xlnx,rxvlan-tag = < 0x00 >;
+ xlnx,rxvlan-tran = < 0x00 >;
+ xlnx,stats = < 0x00 >;
+ xlnx,txcsum = < 0x00 >;
+ xlnx,txmem = < 0x1000 >;
+ xlnx,txvlan-strp = < 0x00 >;
+ xlnx,txvlan-tag = < 0x00 >;
+ xlnx,txvlan-tran = < 0x00 >;
+ xlnx,type = < 0x02 >;
+
+ mdio {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x00 >;
+
+ phy7: phy@7 {
+ compatible = "marvell,88e1111";
+ device_type = "ethernet-phy";
+ reg = < 0x07 >;
+ };
+ };
+ };
+
+ axi_dma: axi-dma@84600000 {
+ compatible = "xlnx,axi-dma-3.00.a";
+ interrupt-parent = < &intc >;
+ interrupts = < 0x01 0x02 0x00 0x02 >;
+ reg = < 0x84600000 0x10000 >;
+ xlnx,dlytmr-resolution = < 0x4e2 >;
+ xlnx,family = "virtex6";
+ xlnx,include-mm2s = < 0x01 >;
+ xlnx,include-mm2s-dre = < 0x01 >;
+ xlnx,include-s2mm = < 0x01 >;
+ xlnx,include-s2mm-dre = < 0x01 >;
+ xlnx,mm2s-burst-size = < 0x10 >;
+ xlnx,prmry-is-aclk-async = < 0x00 >;
+ xlnx,s2mm-burst-size = < 0x10 >;
+ xlnx,sg-include-desc-queue = < 0x01 >;
+ xlnx,sg-include-stscntrl-strm = < 0x01 >;
+ xlnx,sg-length-width = < 0x10 >;
+ xlnx,sg-use-stsapp-length = < 0x01 >;
+ };
+
+ serial@83e00000 {
+ clock-frequency = < 0x5f5e100 >;
+ compatible = "xlnx,axi-uart16550-1.01.a\0xlnx,xps-uart16550-2.00.a\0ns16550a";
+ current-speed = < 0x2580 >;
+ device_type = "serial";
+ interrupt-parent = < &intc >;
+ interrupts = < 0x05 0x02 >;
+ reg = < 0x83e00000 0x10000 >;
+ reg-offset = < 0x1000 >;
+ reg-shift = < 0x02 >;
+ xlnx,external-xin-clk-hz = < 0x17d7840 >;
+ xlnx,family = "virtex6";
+ xlnx,has-external-rclk = < 0x00 >;
+ xlnx,has-external-xin = < 0x00 >;
+ xlnx,is-a-16550 = < 0x01 >;
+ xlnx,use-modem-ports = < 0x00 >;
+ xlnx,use-user-ports = < 0x00 >;
+ };
+
+ system-timer@83c00000 {
+ clock-frequency = < 0x5f5e100 >;
+ compatible = "xlnx,axi-timer-1.01.a\0xlnx,xps-timer-1.00.a";
+ interrupt-parent = < &intc >;
+ interrupts = < 0x02 0x00 >;
+ reg = < 0x83c00000 0x10000 >;
+ xlnx,count-width = < 0x20 >;
+ xlnx,family = "virtex6";
+ xlnx,gen0-assert = < 0x01 >;
+ xlnx,gen1-assert = < 0x01 >;
+ xlnx,one-timer-only = < 0x00 >;
+ xlnx,trig0-assert = < 0x01 >;
+ xlnx,trig1-assert = < 0x01 >;
+ };
+
+ intc: interrupt-controller@81800000 {
+ #interrupt-cells = < 0x02 >;
+ compatible = "xlnx,axi-intc-1.01.a\0xlnx,xps-intc-1.00.a";
+ interrupt-controller;
+ reg = < 0x81800000 0x10000 >;
+ xlnx,kind-of-intr = < 0x04 >;
+ xlnx,num-intr-inputs = < 0x06 >;
+ };
+
+ flash@86000000 {
+ #address-cells = < 0x01 >;
+ #size-cells = < 0x01 >;
+ bank-width = < 0x02 >;
+ compatible = "xlnx,axi-emc-1.01.a\0cfi-flash";
+ reg = < 0x86000000 0x2000000 >;
+ xlnx,axi-clk-period-ps = < 0x2710 >;
+ xlnx,family = "virtex6";
+ xlnx,include-datawidth-matching-0 = < 0x01 >;
+ xlnx,include-datawidth-matching-1 = < 0x00 >;
+ xlnx,include-datawidth-matching-2 = < 0x00 >;
+ xlnx,include-datawidth-matching-3 = < 0x00 >;
+ xlnx,include-negedge-ioregs = < 0x00 >;
+ xlnx,max-mem-width = < 0x10 >;
+ xlnx,mem0-type = < 0x02 >;
+ xlnx,mem0-width = < 0x10 >;
+ xlnx,mem1-type = < 0x00 >;
+ xlnx,mem1-width = < 0x20 >;
+ xlnx,mem2-type = < 0x00 >;
+ xlnx,mem2-width = < 0x20 >;
+ xlnx,mem3-type = < 0x00 >;
+ xlnx,mem3-width = < 0x20 >;
+ xlnx,num-banks-mem = < 0x01 >;
+ xlnx,parity-type-mem-0 = < 0x00 >;
+ xlnx,parity-type-mem-1 = < 0x00 >;
+ xlnx,parity-type-mem-2 = < 0x00 >;
+ xlnx,parity-type-mem-3 = < 0x00 >;
+ xlnx,s-axi-en-reg = < 0x00 >;
+ xlnx,s-axi-mem-addr-width = < 0x20 >;
+ xlnx,s-axi-mem-data-width = < 0x20 >;
+ xlnx,s-axi-mem-id-width = < 0x01 >;
+ xlnx,s-axi-mem-protocol = "AXI4LITE";
+ xlnx,s-axi-reg-addr-width = < 0x20 >;
+ xlnx,s-axi-reg-data-width = < 0x20 >;
+ xlnx,s-axi-reg-protocol = "axi4";
+ xlnx,synch-pipedelay-0 = < 0x02 >;
+ xlnx,synch-pipedelay-1 = < 0x02 >;
+ xlnx,synch-pipedelay-2 = < 0x02 >;
+ xlnx,synch-pipedelay-3 = < 0x02 >;
+ xlnx,tavdv-ps-mem-0 = < 0x1fbd0 >;
+ xlnx,tavdv-ps-mem-1 = < 0x3a98 >;
+ xlnx,tavdv-ps-mem-2 = < 0x3a98 >;
+ xlnx,tavdv-ps-mem-3 = < 0x3a98 >;
+ xlnx,tcedv-ps-mem-0 = < 0x1fbd0 >;
+ xlnx,tcedv-ps-mem-1 = < 0x3a98 >;
+ xlnx,tcedv-ps-mem-2 = < 0x3a98 >;
+ xlnx,tcedv-ps-mem-3 = < 0x3a98 >;
+ xlnx,thzce-ps-mem-0 = < 0x88b8 >;
+ xlnx,thzce-ps-mem-1 = < 0x1b58 >;
+ xlnx,thzce-ps-mem-2 = < 0x1b58 >;
+ xlnx,thzce-ps-mem-3 = < 0x1b58 >;
+ xlnx,thzoe-ps-mem-0 = < 0x1b58 >;
+ xlnx,thzoe-ps-mem-1 = < 0x1b58 >;
+ xlnx,thzoe-ps-mem-2 = < 0x1b58 >;
+ xlnx,thzoe-ps-mem-3 = < 0x1b58 >;
+ xlnx,tlzwe-ps-mem-0 = < 0x88b8 >;
+ xlnx,tlzwe-ps-mem-1 = < 0x00 >;
+ xlnx,tlzwe-ps-mem-2 = < 0x00 >;
+ xlnx,tlzwe-ps-mem-3 = < 0x00 >;
+ xlnx,tpacc-ps-flash-0 = < 0x61a8 >;
+ xlnx,tpacc-ps-flash-1 = < 0x61a8 >;
+ xlnx,tpacc-ps-flash-2 = < 0x61a8 >;
+ xlnx,tpacc-ps-flash-3 = < 0x61a8 >;
+ xlnx,twc-ps-mem-0 = < 0x32c8 >;
+ xlnx,twc-ps-mem-1 = < 0x3a98 >;
+ xlnx,twc-ps-mem-2 = < 0x3a98 >;
+ xlnx,twc-ps-mem-3 = < 0x3a98 >;
+ xlnx,twp-ps-mem-0 = < 0x11170 >;
+ xlnx,twp-ps-mem-1 = < 0x2ee0 >;
+ xlnx,twp-ps-mem-2 = < 0x2ee0 >;
+ xlnx,twp-ps-mem-3 = < 0x2ee0 >;
+ xlnx,twph-ps-mem-0 = < 0x2ee0 >;
+ xlnx,twph-ps-mem-1 = < 0x2ee0 >;
+ xlnx,twph-ps-mem-2 = < 0x2ee0 >;
+ xlnx,twph-ps-mem-3 = < 0x2ee0 >;
+
+ partition@0 {
+ label = "fpga";
+ reg = < 0x00 0x100000 >;
+ };
+
+ partition@100000 {
+ label = "boot";
+ reg = < 0x100000 0x40000 >;
+ };
+
+ partition@140000 {
+ label = "bootenv";
+ reg = < 0x140000 0x20000 >;
+ };
+
+ partition@160000 {
+ label = "config";
+ reg = < 0x160000 0x20000 >;
+ };
+
+ partition@180000 {
+ label = "image";
+ reg = < 0x180000 0xa00000 >;
+ };
+
+ partition@b80000 {
+ label = "spare";
+ reg = < 0xb80000 0x00 >;
+ };
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PULL v1 8/8] microblaze: petalogix-s3adsp1800: Add device-tree source
2020-08-24 10:00 [PULL v1 0/8] Xilinx queue 2020-08-14 Edgar E. Iglesias
` (6 preceding siblings ...)
2020-08-24 10:00 ` [PULL v1 7/8] microblaze: petalogix-ml605: Add device-tree source Edgar E. Iglesias
@ 2020-08-24 10:00 ` Edgar E. Iglesias
2020-08-24 15:32 ` [PULL v1 0/8] Xilinx queue 2020-08-14 Peter Maydell
8 siblings, 0 replies; 10+ messages in thread
From: Edgar E. Iglesias @ 2020-08-24 10:00 UTC (permalink / raw)
To: qemu-devel; +Cc: edgar.iglesias, peter.maydell
From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
Add a device-tree source for petalogix-s3adsp1800 and
recompile the DTB.
This also removes the unused mpmc node which causes
compilation warnings.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
---
pc-bios/petalogix-s3adsp1800.dtb | Bin 8259 -> 8161 bytes
pc-bios/petalogix-s3adsp1800.dts | 282 +++++++++++++++++++++++++++++++
2 files changed, 282 insertions(+)
create mode 100644 pc-bios/petalogix-s3adsp1800.dts
diff --git a/pc-bios/petalogix-s3adsp1800.dtb b/pc-bios/petalogix-s3adsp1800.dtb
index 8ac80f2f2d191a8491b71182be50b3df2989551d..2513599438bffca96a93e877a1981efdd1a91115 100644
GIT binary patch
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diff --git a/pc-bios/petalogix-s3adsp1800.dts b/pc-bios/petalogix-s3adsp1800.dts
new file mode 100644
index 0000000000..f53c36f870
--- /dev/null
+++ b/pc-bios/petalogix-s3adsp1800.dts
@@ -0,0 +1,282 @@
+/*
+ * Copyright (c) 2020 Xilinx Inc.
+ * Written by Edgar E. Iglesias <edgar.iglesias@xilinx.com>.
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+/dts-v1/;
+
+/ {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "xlnx,microblaze";
+ model = "testing";
+
+ memory@90000000 {
+ device_type = "memory";
+ reg = <0x90000000 0x8000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyUL0,115200";
+ stdout-path = "/plb/serial@84000000";
+ };
+
+ cpus {
+ #address-cells = <0x01>;
+ #size-cells = <0x00>;
+ #cpus = <0x01>;
+
+ cpu@0 {
+ clock-frequency = <0x3b9aca0>;
+ compatible = "xlnx,microblaze-7.10.d";
+ d-cache-baseaddr = <0x90000000>;
+ d-cache-highaddr = <0x97ffffff>;
+ d-cache-line-size = <0x10>;
+ d-cache-size = <0x800>;
+ device_type = "cpu";
+ i-cache-baseaddr = <0x90000000>;
+ i-cache-highaddr = <0x97ffffff>;
+ i-cache-line-size = <0x10>;
+ i-cache-size = <0x800>;
+ model = "microblaze,7.10.d";
+ reg = <0x00>;
+ timebase-frequency = <0x3b9aca0>;
+ xlnx,addr-tag-bits = <0x10>;
+ xlnx,allow-dcache-wr = <0x01>;
+ xlnx,allow-icache-wr = <0x01>;
+ xlnx,area-optimized = <0x00>;
+ xlnx,cache-byte-size = <0x800>;
+ xlnx,d-lmb = <0x01>;
+ xlnx,d-opb = <0x00>;
+ xlnx,d-plb = <0x01>;
+ xlnx,data-size = <0x20>;
+ xlnx,dcache-addr-tag = <0x10>;
+ xlnx,dcache-always-used = <0x00>;
+ xlnx,dcache-byte-size = <0x800>;
+ xlnx,dcache-line-len = <0x04>;
+ xlnx,dcache-use-fsl = <0x01>;
+ xlnx,debug-enabled = <0x01>;
+ xlnx,div-zero-exception = <0x00>;
+ xlnx,dopb-bus-exception = <0x00>;
+ xlnx,dynamic-bus-sizing = <0x01>;
+ xlnx,edge-is-positive = <0x01>;
+ xlnx,family = "spartan3adsp";
+ xlnx,fpu-exception = <0x00>;
+ xlnx,fsl-data-size = <0x20>;
+ xlnx,fsl-exception = <0x00>;
+ xlnx,fsl-links = <0x00>;
+ xlnx,i-lmb = <0x01>;
+ xlnx,i-opb = <0x00>;
+ xlnx,i-plb = <0x01>;
+ xlnx,icache-always-used = <0x00>;
+ xlnx,icache-line-len = <0x04>;
+ xlnx,icache-use-fsl = <0x01>;
+ xlnx,ill-opcode-exception = <0x00>;
+ xlnx,instance = "microblaze_0";
+ xlnx,interconnect = <0x01>;
+ xlnx,interrupt-is-edge = <0x00>;
+ xlnx,iopb-bus-exception = <0x00>;
+ xlnx,mmu-dtlb-size = <0x04>;
+ xlnx,mmu-itlb-size = <0x02>;
+ xlnx,mmu-tlb-access = <0x03>;
+ xlnx,mmu-zones = <0x10>;
+ xlnx,number-of-pc-brk = <0x03>;
+ xlnx,number-of-rd-addr-brk = <0x02>;
+ xlnx,number-of-wr-addr-brk = <0x02>;
+ xlnx,opcode-0x0-illegal = <0x00>;
+ xlnx,pvr = <0x01>;
+ xlnx,pvr-user1 = <0x00>;
+ xlnx,pvr-user2 = <0x00>;
+ xlnx,reset-msr = <0x00>;
+ xlnx,sco = <0x00>;
+ xlnx,unaligned-exceptions = <0x01>;
+ xlnx,use-barrel = <0x01>;
+ xlnx,use-dcache = <0x01>;
+ xlnx,use-div = <0x00>;
+ xlnx,use-ext-brk = <0x01>;
+ xlnx,use-ext-nm-brk = <0x01>;
+ xlnx,use-extended-fsl-instr = <0x00>;
+ xlnx,use-fpu = <0x00>;
+ xlnx,use-hw-mul = <0x01>;
+ xlnx,use-icache = <0x01>;
+ xlnx,use-interrupt = <0x01>;
+ xlnx,use-mmu = <0x03>;
+ xlnx,use-msr-instr = <0x01>;
+ xlnx,use-pcmp-instr = <0x01>;
+ };
+ };
+
+ plb {
+ #address-cells = <0x01>;
+ #size-cells = <0x01>;
+ compatible = "xlnx,plb-v46-1.03.a\0simple-bus";
+ ranges;
+
+ ethernet@81000000 {
+ compatible = "xlnx,xps-ethernetlite-2.00.a";
+ device_type = "network";
+ interrupt-parent = <0x01>;
+ interrupts = <0x01 0x00>;
+ local-mac-address = [02 00 00 00 00 00];
+ reg = <0x81000000 0x10000>;
+ xlnx,duplex = <0x01>;
+ xlnx,family = "spartan3adsp";
+ xlnx,rx-ping-pong = <0x00>;
+ xlnx,tx-ping-pong = <0x00>;
+ };
+
+ flash@a0000000 {
+ bank-width = <0x01>;
+ compatible = "xlnx,xps-mch-emc-2.00.a\0cfi-flash";
+ reg = <0xa0000000 0x1000000>;
+ xlnx,family = "spartan3adsp";
+ xlnx,include-datawidth-matching-0 = <0x01>;
+ xlnx,include-datawidth-matching-1 = <0x00>;
+ xlnx,include-datawidth-matching-2 = <0x00>;
+ xlnx,include-datawidth-matching-3 = <0x00>;
+ xlnx,include-negedge-ioregs = <0x00>;
+ xlnx,include-plb-ipif = <0x01>;
+ xlnx,include-wrbuf = <0x01>;
+ xlnx,max-mem-width = <0x08>;
+ xlnx,mch-native-dwidth = <0x20>;
+ xlnx,mch-plb-clk-period-ps = <0x3e80>;
+ xlnx,mch-splb-awidth = <0x20>;
+ xlnx,mch0-accessbuf-depth = <0x10>;
+ xlnx,mch0-protocol = <0x00>;
+ xlnx,mch0-rddatabuf-depth = <0x10>;
+ xlnx,mch1-accessbuf-depth = <0x10>;
+ xlnx,mch1-protocol = <0x00>;
+ xlnx,mch1-rddatabuf-depth = <0x10>;
+ xlnx,mch2-accessbuf-depth = <0x10>;
+ xlnx,mch2-protocol = <0x00>;
+ xlnx,mch2-rddatabuf-depth = <0x10>;
+ xlnx,mch3-accessbuf-depth = <0x10>;
+ xlnx,mch3-protocol = <0x00>;
+ xlnx,mch3-rddatabuf-depth = <0x10>;
+ xlnx,mem0-width = <0x08>;
+ xlnx,mem1-width = <0x20>;
+ xlnx,mem2-width = <0x20>;
+ xlnx,mem3-width = <0x20>;
+ xlnx,num-banks-mem = <0x01>;
+ xlnx,num-channels = <0x00>;
+ xlnx,priority-mode = <0x00>;
+ xlnx,synch-mem-0 = <0x00>;
+ xlnx,synch-mem-1 = <0x00>;
+ xlnx,synch-mem-2 = <0x00>;
+ xlnx,synch-mem-3 = <0x00>;
+ xlnx,synch-pipedelay-0 = <0x02>;
+ xlnx,synch-pipedelay-1 = <0x02>;
+ xlnx,synch-pipedelay-2 = <0x02>;
+ xlnx,synch-pipedelay-3 = <0x02>;
+ xlnx,tavdv-ps-mem-0 = <0x11170>;
+ xlnx,tavdv-ps-mem-1 = <0x3a98>;
+ xlnx,tavdv-ps-mem-2 = <0x3a98>;
+ xlnx,tavdv-ps-mem-3 = <0x3a98>;
+ xlnx,tcedv-ps-mem-0 = <0x11170>;
+ xlnx,tcedv-ps-mem-1 = <0x3a98>;
+ xlnx,tcedv-ps-mem-2 = <0x3a98>;
+ xlnx,tcedv-ps-mem-3 = <0x3a98>;
+ xlnx,thzce-ps-mem-0 = <0x61a8>;
+ xlnx,thzce-ps-mem-1 = <0x1b58>;
+ xlnx,thzce-ps-mem-2 = <0x1b58>;
+ xlnx,thzce-ps-mem-3 = <0x1b58>;
+ xlnx,thzoe-ps-mem-0 = <0x61a8>;
+ xlnx,thzoe-ps-mem-1 = <0x1b58>;
+ xlnx,thzoe-ps-mem-2 = <0x1b58>;
+ xlnx,thzoe-ps-mem-3 = <0x1b58>;
+ xlnx,tlzwe-ps-mem-0 = <0x1388>;
+ xlnx,tlzwe-ps-mem-1 = <0x00>;
+ xlnx,tlzwe-ps-mem-2 = <0x00>;
+ xlnx,tlzwe-ps-mem-3 = <0x00>;
+ xlnx,twc-ps-mem-0 = <0x11170>;
+ xlnx,twc-ps-mem-1 = <0x3a98>;
+ xlnx,twc-ps-mem-2 = <0x3a98>;
+ xlnx,twc-ps-mem-3 = <0x3a98>;
+ xlnx,twp-ps-mem-0 = <0xafc8>;
+ xlnx,twp-ps-mem-1 = <0x2ee0>;
+ xlnx,twp-ps-mem-2 = <0x2ee0>;
+ xlnx,twp-ps-mem-3 = <0x2ee0>;
+ xlnx,xcl0-linesize = <0x04>;
+ xlnx,xcl0-writexfer = <0x01>;
+ xlnx,xcl1-linesize = <0x04>;
+ xlnx,xcl1-writexfer = <0x01>;
+ xlnx,xcl2-linesize = <0x04>;
+ xlnx,xcl2-writexfer = <0x01>;
+ xlnx,xcl3-linesize = <0x04>;
+ xlnx,xcl3-writexfer = <0x01>;
+ };
+
+ gpio@81400000 {
+ compatible = "xlnx,xps-gpio-1.00.a";
+ interrupt-parent = <0x01>;
+ interrupts = <0x02 0x02>;
+ reg = <0x81400000 0x10000>;
+ xlnx,all-inputs = <0x00>;
+ xlnx,all-inputs-2 = <0x00>;
+ xlnx,dout-default = <0x00>;
+ xlnx,dout-default-2 = <0x00>;
+ xlnx,family = "spartan3adsp";
+ xlnx,gpio-width = <0x08>;
+ xlnx,interrupt-present = <0x01>;
+ xlnx,is-bidir = <0x00>;
+ xlnx,is-bidir-2 = <0x01>;
+ xlnx,is-dual = <0x00>;
+ xlnx,tri-default = <0xffffffff>;
+ xlnx,tri-default-2 = <0xffffffff>;
+ };
+
+ serial@84000000 {
+ clock-frequency = <0x3b9aca0>;
+ compatible = "xlnx,xps-uartlite-1.00.a";
+ current-speed = <0x1c200>;
+ device_type = "serial";
+ interrupt-parent = <0x01>;
+ interrupts = <0x03 0x00>;
+ port-number = <0x00>;
+ reg = <0x84000000 0x10000>;
+ xlnx,baudrate = <0x1c200>;
+ xlnx,data-bits = <0x08>;
+ xlnx,family = "spartan3adsp";
+ xlnx,odd-parity = <0x00>;
+ xlnx,use-parity = <0x00>;
+ };
+
+ debug@84400000 {
+ compatible = "xlnx,mdm-1.00.d";
+ reg = <0x84400000 0x10000>;
+ xlnx,family = "spartan3adsp";
+ xlnx,interconnect = <0x01>;
+ xlnx,jtag-chain = <0x02>;
+ xlnx,mb-dbg-ports = <0x01>;
+ xlnx,uart-width = <0x08>;
+ xlnx,use-uart = <0x01>;
+ xlnx,write-fsl-ports = <0x00>;
+ };
+
+ interrupt-controller@81800000 {
+ #interrupt-cells = <0x02>;
+ compatible = "xlnx,xps-intc-1.00.a";
+ interrupt-controller;
+ reg = <0x81800000 0x10000>;
+ xlnx,kind-of-intr = <0x0a>;
+ xlnx,num-intr-inputs = <0x04>;
+ linux,phandle = <0x01>;
+ };
+
+ timer@83c00000 {
+ compatible = "xlnx,xps-timer-1.00.a";
+ interrupt-parent = <0x01>;
+ interrupts = <0x00 0x02>;
+ reg = <0x83c00000 0x10000>;
+ xlnx,count-width = <0x20>;
+ xlnx,family = "spartan3adsp";
+ xlnx,gen0-assert = <0x01>;
+ xlnx,gen1-assert = <0x01>;
+ xlnx,one-timer-only = <0x00>;
+ xlnx,trig0-assert = <0x01>;
+ xlnx,trig1-assert = <0x01>;
+ };
+ };
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PULL v1 0/8] Xilinx queue 2020-08-14
2020-08-24 10:00 [PULL v1 0/8] Xilinx queue 2020-08-14 Edgar E. Iglesias
` (7 preceding siblings ...)
2020-08-24 10:00 ` [PULL v1 8/8] microblaze: petalogix-s3adsp1800: " Edgar E. Iglesias
@ 2020-08-24 15:32 ` Peter Maydell
8 siblings, 0 replies; 10+ messages in thread
From: Peter Maydell @ 2020-08-24 15:32 UTC (permalink / raw)
To: Edgar E. Iglesias; +Cc: Edgar Iglesias, QEMU Developers
On Mon, 24 Aug 2020 at 11:00, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@xilinx.com>
>
> The following changes since commit 8367a77c4d3f6e1e60890f5510304feb2c621611:
>
> Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.2-pull-request' into staging (2020-08-23 16:34:43 +0100)
>
> are available in the Git repository at:
>
> git@github.com:edgarigl/qemu.git tags/edgar/xilinx-next-2020-08-24.for-upstream
>
> for you to fetch changes up to 43f4e3d4fa2f9dba6bd68452a3380864ad9453c1:
>
> microblaze: petalogix-s3adsp1800: Add device-tree source (2020-08-24 10:47:27 +0200)
>
> ----------------------------------------------------------------
> For upstream.
>
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/5.2
for any user-visible changes.
-- PMM
^ permalink raw reply [flat|nested] 10+ messages in thread