From: Alistair Francis <alistair.francis@wdc.com>
To: qemu-devel@nongnu.org
Cc: Palmer Dabbelt <palmerdabbelt@google.com>,
alistair23@gmail.com, Anup Patel <anup.patel@wdc.com>,
alistair.francis@wdc.com
Subject: [PULL 01/18] hw/riscv: Allow creating multiple instances of CLINT
Date: Tue, 25 Aug 2020 11:48:19 -0700 [thread overview]
Message-ID: <20200825184836.1282371-2-alistair.francis@wdc.com> (raw)
In-Reply-To: <20200825184836.1282371-1-alistair.francis@wdc.com>
From: Anup Patel <anup.patel@wdc.com>
We extend CLINT emulation to allow multiple instances of CLINT in
a QEMU RISC-V machine. To achieve this, we remove first HART id
zero assumption from CLINT emulation.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Message-Id: <20200616032229.766089-2-anup.patel@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
include/hw/riscv/sifive_clint.h | 7 ++++---
hw/riscv/sifive_clint.c | 20 ++++++++++++--------
hw/riscv/sifive_e.c | 2 +-
hw/riscv/sifive_u.c | 2 +-
hw/riscv/spike.c | 2 +-
hw/riscv/virt.c | 2 +-
6 files changed, 20 insertions(+), 15 deletions(-)
diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clint.h
index 4a720bfece..9f5fb3d31d 100644
--- a/include/hw/riscv/sifive_clint.h
+++ b/include/hw/riscv/sifive_clint.h
@@ -33,6 +33,7 @@ typedef struct SiFiveCLINTState {
/*< public >*/
MemoryRegion mmio;
+ uint32_t hartid_base;
uint32_t num_harts;
uint32_t sip_base;
uint32_t timecmp_base;
@@ -40,9 +41,9 @@ typedef struct SiFiveCLINTState {
uint32_t aperture_size;
} SiFiveCLINTState;
-DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
- uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base,
- bool provide_rdtime);
+DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
+ uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
+ uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime);
enum {
SIFIVE_SIP_BASE = 0x0,
diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c
index 669c21adc2..15e13d5f7a 100644
--- a/hw/riscv/sifive_clint.c
+++ b/hw/riscv/sifive_clint.c
@@ -79,7 +79,7 @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
SiFiveCLINTState *clint = opaque;
if (addr >= clint->sip_base &&
addr < clint->sip_base + (clint->num_harts << 2)) {
- size_t hartid = (addr - clint->sip_base) >> 2;
+ size_t hartid = clint->hartid_base + ((addr - clint->sip_base) >> 2);
CPUState *cpu = qemu_get_cpu(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
@@ -92,7 +92,8 @@ static uint64_t sifive_clint_read(void *opaque, hwaddr addr, unsigned size)
}
} else if (addr >= clint->timecmp_base &&
addr < clint->timecmp_base + (clint->num_harts << 3)) {
- size_t hartid = (addr - clint->timecmp_base) >> 3;
+ size_t hartid = clint->hartid_base +
+ ((addr - clint->timecmp_base) >> 3);
CPUState *cpu = qemu_get_cpu(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
@@ -129,7 +130,7 @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
if (addr >= clint->sip_base &&
addr < clint->sip_base + (clint->num_harts << 2)) {
- size_t hartid = (addr - clint->sip_base) >> 2;
+ size_t hartid = clint->hartid_base + ((addr - clint->sip_base) >> 2);
CPUState *cpu = qemu_get_cpu(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
@@ -142,7 +143,8 @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value,
return;
} else if (addr >= clint->timecmp_base &&
addr < clint->timecmp_base + (clint->num_harts << 3)) {
- size_t hartid = (addr - clint->timecmp_base) >> 3;
+ size_t hartid = clint->hartid_base +
+ ((addr - clint->timecmp_base) >> 3);
CPUState *cpu = qemu_get_cpu(hartid);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
@@ -186,6 +188,7 @@ static const MemoryRegionOps sifive_clint_ops = {
};
static Property sifive_clint_properties[] = {
+ DEFINE_PROP_UINT32("hartid-base", SiFiveCLINTState, hartid_base, 0),
DEFINE_PROP_UINT32("num-harts", SiFiveCLINTState, num_harts, 0),
DEFINE_PROP_UINT32("sip-base", SiFiveCLINTState, sip_base, 0),
DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0),
@@ -227,13 +230,13 @@ type_init(sifive_clint_register_types)
/*
* Create CLINT device.
*/
-DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
- uint32_t sip_base, uint32_t timecmp_base, uint32_t time_base,
- bool provide_rdtime)
+DeviceState *sifive_clint_create(hwaddr addr, hwaddr size,
+ uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base,
+ uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime)
{
int i;
for (i = 0; i < num_harts; i++) {
- CPUState *cpu = qemu_get_cpu(i);
+ CPUState *cpu = qemu_get_cpu(hartid_base + i);
CPURISCVState *env = cpu ? cpu->env_ptr : NULL;
if (!env) {
continue;
@@ -247,6 +250,7 @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t num_harts,
}
DeviceState *dev = qdev_new(TYPE_SIFIVE_CLINT);
+ qdev_prop_set_uint32(dev, "hartid-base", hartid_base);
qdev_prop_set_uint32(dev, "num-harts", num_harts);
qdev_prop_set_uint32(dev, "sip-base", sip_base);
qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base);
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index c8b060486a..01f661d00c 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -211,7 +211,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
SIFIVE_E_PLIC_CONTEXT_STRIDE,
memmap[SIFIVE_E_PLIC].size);
sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
- memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
+ memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
create_unimplemented_device("riscv.sifive.e.aon",
memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 18301e6fa5..8d2ee9d026 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -703,7 +703,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
- memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
+ memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 13958bdbeb..5d422b4944 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -234,7 +234,7 @@ static void spike_board_init(MachineState *machine)
/* Core Local Interruptor (timer and IPI) */
sifive_clint_create(memmap[SPIKE_CLINT].base, memmap[SPIKE_CLINT].size,
- smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
+ 0, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE,
false);
}
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 6e91cf129e..69cfca8501 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -571,7 +571,7 @@ static void virt_machine_init(MachineState *machine)
VIRT_PLIC_CONTEXT_STRIDE,
memmap[VIRT_PLIC].size);
sifive_clint_create(memmap[VIRT_CLINT].base,
- memmap[VIRT_CLINT].size, smp_cpus,
+ memmap[VIRT_CLINT].size, 0, smp_cpus,
SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true);
sifive_test_create(memmap[VIRT_TEST].base);
--
2.28.0
next prev parent reply other threads:[~2020-08-25 19:02 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-25 18:48 [PULL 00/18] riscv-to-apply queue Alistair Francis
2020-08-25 18:48 ` Alistair Francis [this message]
2020-08-25 18:48 ` [PULL 02/18] hw/riscv: Allow creating multiple instances of PLIC Alistair Francis
2020-08-25 18:48 ` [PULL 03/18] hw/riscv: Add helpers for RISC-V multi-socket NUMA machines Alistair Francis
2020-08-25 18:48 ` [PULL 04/18] hw/riscv: spike: Allow creating multiple NUMA sockets Alistair Francis
2020-08-25 18:48 ` [PULL 05/18] hw/riscv: virt: " Alistair Francis
2021-08-09 9:46 ` Peter Maydell
2021-08-12 14:57 ` Peter Maydell
2020-08-25 18:48 ` [PULL 06/18] target/riscv: Allow setting a two-stage lookup in the virt status Alistair Francis
2020-08-25 18:48 ` [PULL 07/18] target/riscv: Allow generating hlv/hlvx/hsv instructions Alistair Francis
2020-08-25 18:48 ` [PULL 08/18] target/riscv: Do two-stage lookups on " Alistair Francis
2020-08-25 18:48 ` [PULL 09/18] target/riscv: Don't allow guest to write to htinst Alistair Francis
2020-08-25 18:48 ` [PULL 10/18] target/riscv: Convert MSTATUS MTL to GVA Alistair Francis
2020-08-25 18:48 ` [PULL 11/18] target/riscv: Fix the interrupt cause code Alistair Francis
2020-08-25 18:48 ` [PULL 12/18] target/riscv: Update the Hypervisor trap return/entry Alistair Francis
2020-08-25 18:48 ` [PULL 13/18] target/riscv: Update the CSRs to the v0.6 Hyp extension Alistair Francis
2020-08-25 18:48 ` [PULL 14/18] target/riscv: Only support a single VSXL length Alistair Francis
2020-08-25 18:48 ` [PULL 15/18] target/riscv: Only support little endian guests Alistair Francis
2020-08-25 18:48 ` [PULL 16/18] target/riscv: Support the v0.6 Hypervisor extension CRSs Alistair Francis
2020-08-25 18:48 ` [PULL 17/18] target/riscv: Return the exception from invalid CSR accesses Alistair Francis
2020-08-25 18:48 ` [PULL 18/18] target/riscv: Support the Virtual Instruction fault Alistair Francis
2020-08-25 21:24 ` [PULL 00/18] riscv-to-apply queue Peter Maydell
2020-08-25 21:21 ` Alistair Francis
2020-08-25 21:49 ` Peter Maydell
2020-08-25 22:30 ` Alistair Francis
2020-08-26 3:21 ` Bin Meng
2020-08-26 9:25 ` Peter Maydell
2020-08-26 10:06 ` Bin Meng
2020-08-27 15:44 ` Alistair Francis
2020-08-29 15:49 ` LIU Zhiwei
2020-08-29 17:30 ` Alistair Francis
2020-08-26 9:28 ` Peter Maydell
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