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[216.228.167.147]) by smtp.gmail.com with ESMTPSA id k4sm16074pgr.87.2020.08.25.14.00.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Aug 2020 14:00:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/77] target/microblaze: Split out EDR from env->sregs Date: Tue, 25 Aug 2020 13:58:44 -0700 Message-Id: <20200825205950.730499-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org> References: <20200825205950.730499-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: edgar.iglesias@gmail.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Finish eliminating the sregs array in favor of individual members. Does not correct the width of EDR, yet. Signed-off-by: Richard Henderson --- target/microblaze/cpu.h | 2 +- linux-user/elfload.c | 9 ++++++--- target/microblaze/gdbstub.c | 4 ++-- target/microblaze/translate.c | 16 +++------------- 4 files changed, 12 insertions(+), 19 deletions(-) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index deddb47abb..610ddfb719 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -242,7 +242,7 @@ struct CPUMBState { uint64_t esr; uint64_t fsr; uint64_t btr; - uint64_t sregs[14]; + uint64_t edr; float_status fp_status; /* Stack protectors. Yes, it's a hw feature. */ uint32_t slr, shr; diff --git a/linux-user/elfload.c b/linux-user/elfload.c index fe9dfe795d..bbfb665321 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1032,9 +1032,12 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMBState *env (*regs)[pos++] = tswapreg(env->regs[i]); } - for (i = 0; i < 6; i++) { - (*regs)[pos++] = tswapreg(env->sregs[i]); - } + (*regs)[pos++] = tswapreg(env->pc); + (*regs)[pos++] = tswapreg(env->msr); + (*regs)[pos++] = 0; + (*regs)[pos++] = tswapreg(env->ear); + (*regs)[pos++] = 0; + (*regs)[pos++] = tswapreg(env->esr); } #endif /* TARGET_MICROBLAZE */ diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c index cde8c169bf..9cba9d2215 100644 --- a/target/microblaze/gdbstub.c +++ b/target/microblaze/gdbstub.c @@ -81,7 +81,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n) val = env->pvr.regs[n - GDB_PVR0]; break; case GDB_EDR: - val = env->sregs[SR_EDR]; + val = env->edr; break; case GDB_SLR: val = env->slr; @@ -137,7 +137,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) env->pvr.regs[n - GDB_PVR0] = tmp; break; case GDB_EDR: - env->sregs[SR_EDR] = tmp; + env->edr = tmp; break; case GDB_SLR: env->slr = tmp; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 469e1f103a..7d307e6b48 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -103,12 +103,6 @@ static const char *regnames[] = "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", }; -static const char *special_regnames[] = -{ - "rpc", "rmsr", "sr2", "rear", "sr4", "resr", "sr6", "rfsr", - "sr8", "sr9", "sr10", "rbtr", "sr12", "redr" -}; - static inline void t_sync_flags(DisasContext *dc) { /* Synch the tb dependent flags between translator and runtime. */ @@ -1828,7 +1822,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags) /* Registers that aren't modeled are reported as 0 */ qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 " - "rtlblo=0 rtlbhi=0\n", env->sregs[SR_EDR]); + "rtlblo=0 rtlbhi=0\n", env->edr); qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr); for (i = 0; i < 32; i++) { qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]); @@ -1881,12 +1875,8 @@ void mb_tcg_init(void) tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr"); cpu_SR[SR_BTR] = tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr"); - - for (i = SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) { - cpu_SR[i] = tcg_global_mem_new_i64(cpu_env, - offsetof(CPUMBState, sregs[i]), - special_regnames[i]); - } + cpu_SR[SR_EDR] = + tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr"); } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, -- 2.25.1