From: Richard Henderson <richard.henderson@linaro.org>
To: qemu-devel@nongnu.org
Cc: edgar.iglesias@gmail.com
Subject: [PATCH 04/77] target/microblaze: Tidy gdbstub
Date: Tue, 25 Aug 2020 13:58:37 -0700 [thread overview]
Message-ID: <20200825205950.730499-5-richard.henderson@linaro.org> (raw)
In-Reply-To: <20200825205950.730499-1-richard.henderson@linaro.org>
Use an enumeration for the gdb register mapping. Use one
switch statement for the entire dispatch. Drop sreg_map
and simply enumerate those cases explicitly. Force r0 to
have value 0 and ignore writes.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/microblaze/gdbstub.c | 193 +++++++++++++++++++-----------------
1 file changed, 101 insertions(+), 92 deletions(-)
diff --git a/target/microblaze/gdbstub.c b/target/microblaze/gdbstub.c
index 73e8973597..e65ec051a5 100644
--- a/target/microblaze/gdbstub.c
+++ b/target/microblaze/gdbstub.c
@@ -21,58 +21,80 @@
#include "cpu.h"
#include "exec/gdbstub.h"
+/*
+ * GDB expects SREGs in the following order:
+ * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI.
+ *
+ * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't
+ * map them to anything and return a value of 0 instead.
+ */
+
+enum {
+ GDB_PC = 32 + 0,
+ GDB_MSR = 32 + 1,
+ GDB_EAR = 32 + 2,
+ GDB_ESR = 32 + 3,
+ GDB_FSR = 32 + 4,
+ GDB_BTR = 32 + 5,
+ GDB_PVR0 = 32 + 6,
+ GDB_PVR11 = 32 + 17,
+ GDB_EDR = 32 + 18,
+ GDB_SLR = 32 + 25,
+ GDB_SHR = 32 + 26,
+};
+
int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
+ CPUClass *cc = CPU_GET_CLASS(cs);
CPUMBState *env = &cpu->env;
- /*
- * GDB expects SREGs in the following order:
- * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI.
- * They aren't stored in this order, so make a map.
- * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't
- * map them to anything and return a value of 0 instead.
- */
- static const uint8_t sreg_map[6] = {
- SR_PC,
- SR_MSR,
- SR_EAR,
- SR_ESR,
- SR_FSR,
- SR_BTR
- };
+ uint32_t val;
- /*
- * GDB expects registers to be reported in this order:
- * R0-R31
- * PC-BTR
- * PVR0-PVR11
- * EDR-TLBHI
- * SLR-SHR
- */
- if (n < 32) {
- return gdb_get_reg32(mem_buf, env->regs[n]);
- } else {
- n -= 32;
- switch (n) {
- case 0 ... 5:
- return gdb_get_reg32(mem_buf, env->sregs[sreg_map[n]]);
- /* PVR12 is intentionally skipped */
- case 6 ... 17:
- n -= 6;
- return gdb_get_reg32(mem_buf, env->pvr.regs[n]);
- case 18:
- return gdb_get_reg32(mem_buf, env->sregs[SR_EDR]);
- /* Other SRegs aren't modeled, so report a value of 0 */
- case 19 ... 24:
- return gdb_get_reg32(mem_buf, 0);
- case 25:
- return gdb_get_reg32(mem_buf, env->slr);
- case 26:
- return gdb_get_reg32(mem_buf, env->shr);
- default:
- return 0;
- }
+ if (n > cc->gdb_num_core_regs) {
+ return 0;
}
+
+ switch (n) {
+ case 1 ... 31:
+ val = env->regs[n];
+ break;
+ case GDB_PC:
+ val = env->sregs[SR_PC];
+ break;
+ case GDB_MSR:
+ val = env->sregs[SR_MSR];
+ break;
+ case GDB_EAR:
+ val = env->sregs[SR_EAR];
+ break;
+ case GDB_ESR:
+ val = env->sregs[SR_ESR];
+ break;
+ case GDB_FSR:
+ val = env->sregs[SR_FSR];
+ break;
+ case GDB_BTR:
+ val = env->sregs[SR_BTR];
+ break;
+ case GDB_PVR0 ... GDB_PVR11:
+ /* PVR12 is intentionally skipped */
+ val = env->pvr.regs[n - GDB_PVR0];
+ break;
+ case GDB_EDR:
+ val = env->sregs[SR_EDR];
+ break;
+ case GDB_SLR:
+ val = env->slr;
+ break;
+ case GDB_SHR:
+ val = env->shr;
+ break;
+ default:
+ /* Other SRegs aren't modeled, so report a value of 0 */
+ val = 0;
+ break;
+ }
+ return gdb_get_reg32(mem_buf, val);
}
int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
@@ -82,60 +104,47 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
CPUMBState *env = &cpu->env;
uint32_t tmp;
- /*
- * GDB expects SREGs in the following order:
- * PC, MSR, EAR, ESR, FSR, BTR, EDR, PID, ZPR, TLBX, TLBSX, TLBLO, TLBHI.
- * They aren't stored in this order, so make a map.
- * PID, ZPR, TLBx, TLBsx, TLBLO, and TLBHI aren't modeled, so we don't
- * map them to anything.
- */
- static const uint8_t sreg_map[6] = {
- SR_PC,
- SR_MSR,
- SR_EAR,
- SR_ESR,
- SR_FSR,
- SR_BTR
- };
-
if (n > cc->gdb_num_core_regs) {
return 0;
}
tmp = ldl_p(mem_buf);
- /*
- * GDB expects registers to be reported in this order:
- * R0-R31
- * PC-BTR
- * PVR0-PVR11
- * EDR-TLBHI
- * SLR-SHR
- */
- if (n < 32) {
+ switch (n) {
+ case 1 ... 31:
env->regs[n] = tmp;
- } else {
- n -= 32;
- switch (n) {
- case 0 ... 5:
- env->sregs[sreg_map[n]] = tmp;
- break;
+ break;
+ case GDB_PC:
+ env->sregs[SR_PC] = tmp;
+ break;
+ case GDB_MSR:
+ env->sregs[SR_MSR] = tmp;
+ break;
+ case GDB_EAR:
+ env->sregs[SR_EAR] = tmp;
+ break;
+ case GDB_ESR:
+ env->sregs[SR_ESR] = tmp;
+ break;
+ case GDB_FSR:
+ env->sregs[SR_FSR] = tmp;
+ break;
+ case GDB_BTR:
+ env->sregs[SR_BTR] = tmp;
+ break;
+ case GDB_PVR0 ... GDB_PVR11:
/* PVR12 is intentionally skipped */
- case 6 ... 17:
- n -= 6;
- env->pvr.regs[n] = tmp;
- break;
- /* Only EDR is modeled in these indeces, so ignore the rest */
- case 18:
- env->sregs[SR_EDR] = tmp;
- break;
- case 25:
- env->slr = tmp;
- break;
- case 26:
- env->shr = tmp;
- break;
- }
+ env->pvr.regs[n - GDB_PVR0] = tmp;
+ break;
+ case GDB_EDR:
+ env->sregs[SR_EDR] = tmp;
+ break;
+ case GDB_SLR:
+ env->slr = tmp;
+ break;
+ case GDB_SHR:
+ env->shr = tmp;
+ break;
}
return 4;
}
--
2.25.1
next prev parent reply other threads:[~2020-08-25 21:03 UTC|newest]
Thread overview: 102+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-25 20:58 [PATCH 00/77] target/microblaze improvements Richard Henderson
2020-08-25 20:58 ` [PATCH 01/77] tests/tcg: Add microblaze to arches filter Richard Henderson
2020-08-26 16:20 ` Edgar E. Iglesias
2020-08-25 20:58 ` [PATCH 02/77] tests/tcg: Do not require FE_TOWARDZERO Richard Henderson
2020-08-26 16:20 ` Edgar E. Iglesias
2020-08-25 20:58 ` [PATCH 03/77] tests/tcg: Do not require FE_* exception bits Richard Henderson
2020-08-26 16:21 ` Edgar E. Iglesias
2020-08-25 20:58 ` Richard Henderson [this message]
2020-08-25 20:58 ` [PATCH 05/77] target/microblaze: Split out PC from env->sregs Richard Henderson
2020-08-25 20:58 ` [PATCH 06/77] target/microblaze: Split out MSR " Richard Henderson
2020-08-25 20:58 ` [PATCH 07/77] target/microblaze: Split out EAR " Richard Henderson
2020-08-25 20:58 ` [PATCH 08/77] target/microblaze: Split out ESR " Richard Henderson
2020-08-25 20:58 ` [PATCH 09/77] target/microblaze: Split out FSR " Richard Henderson
2020-08-25 20:58 ` [PATCH 10/77] target/microblaze: Split out BTR " Richard Henderson
2020-08-25 20:58 ` [PATCH 11/77] target/microblaze: Split out EDR " Richard Henderson
2020-08-25 20:58 ` [PATCH 12/77] target/microblaze: Split the cpu_SR array Richard Henderson
2020-08-25 20:58 ` [PATCH 13/77] target/microblaze: Fix width of PC and BTARGET Richard Henderson
2020-08-25 20:58 ` [PATCH 14/77] target/microblaze: Fix width of MSR Richard Henderson
2020-08-25 20:58 ` [PATCH 15/77] target/microblaze: Fix width of ESR Richard Henderson
2020-08-25 20:58 ` [PATCH 16/77] target/microblaze: Fix width of FSR Richard Henderson
2020-08-25 20:58 ` [PATCH 17/77] target/microblaze: Fix width of BTR Richard Henderson
2020-08-25 20:58 ` [PATCH 18/77] target/microblaze: Fix width of EDR Richard Henderson
2020-08-25 20:58 ` [PATCH 19/77] target/microblaze: Remove cpu_ear Richard Henderson
2020-08-25 20:58 ` [PATCH 20/77] target/microblaze: Tidy raising of exceptions Richard Henderson
2020-08-25 20:58 ` [PATCH 21/77] target/microblaze: Mark raise_exception as noreturn Richard Henderson
2020-08-25 20:58 ` [PATCH 22/77] target/microblaze: Remove helper_debug and env->debug Richard Henderson
2020-08-25 20:58 ` [PATCH 23/77] target/microblaze: Rename env_* tcg variables to cpu_* Richard Henderson
2020-08-25 20:58 ` [PATCH 24/77] target/microblaze: Tidy mb_tcg_init Richard Henderson
2020-08-25 20:58 ` [PATCH 25/77] target/microblaze: Split out MSR[C] to its own variable Richard Henderson
2020-08-25 20:58 ` [PATCH 26/77] target/microblaze: Use DISAS_NORETURN Richard Henderson
2020-08-25 20:59 ` [PATCH 27/77] target/microblaze: Check singlestep_enabled in gen_goto_tb Richard Henderson
2020-08-25 20:59 ` [PATCH 28/77] target/microblaze: Convert to DisasContextBase Richard Henderson
2020-08-25 20:59 ` [PATCH 29/77] target/microblaze: Convert to translator_loop Richard Henderson
2020-08-25 20:59 ` [PATCH 30/77] target/microblaze: Remove SIM_COMPAT Richard Henderson
2020-08-25 20:59 ` [PATCH 31/77] target/microblaze: Remove DISAS_GNU Richard Henderson
2020-08-25 20:59 ` [PATCH 32/77] target/microblaze: Remove empty D macros Richard Henderson
2020-08-25 20:59 ` [PATCH 33/77] target/microblaze: Remove LOG_DIS Richard Henderson
2020-08-25 20:59 ` [PATCH 34/77] target/microblaze: Ensure imm constant is always available Richard Henderson
2020-08-25 20:59 ` [PATCH 35/77] target/microblaze: Add decodetree infrastructure Richard Henderson
2020-08-25 20:59 ` [PATCH 36/77] target/microblaze: Convert dec_add to decodetree Richard Henderson
2020-08-25 20:59 ` [PATCH 37/77] target/microblaze: Convert dec_sub " Richard Henderson
2020-08-25 20:59 ` [PATCH 38/77] target/microblaze: Implement cmp and cmpu inline Richard Henderson
2020-08-25 20:59 ` [PATCH 39/77] target/microblaze: Convert dec_pattern to decodetree Richard Henderson
2020-08-25 20:59 ` [PATCH 40/77] target/microblaze: Convert dec_and, dec_or, dec_xor " Richard Henderson
2020-08-25 20:59 ` [PATCH 41/77] target/microblaze: Convert dec_mul " Richard Henderson
2020-08-25 20:59 ` [PATCH 42/77] target/microblaze: Convert dec_div " Richard Henderson
2020-08-25 20:59 ` [PATCH 43/77] target/microblaze: Unwind properly when raising divide-by-zero Richard Henderson
2020-08-25 20:59 ` [PATCH 44/77] target/microblaze: Convert dec_bit to decodetree Richard Henderson
2020-08-25 20:59 ` [PATCH 45/77] target/microblaze: Convert dec_barrel " Richard Henderson
2020-08-25 20:59 ` [PATCH 46/77] target/microblaze: Convert dec_imm " Richard Henderson
2020-08-25 20:59 ` [PATCH 47/77] target/microblaze: Convert dec_fpu " Richard Henderson
2020-08-25 20:59 ` [PATCH 48/77] target/microblaze: Fix cpu unwind for fpu exceptions Richard Henderson
2020-08-25 20:59 ` [PATCH 49/77] target/microblaze: Mark fpu helpers TCG_CALL_NO_WG Richard Henderson
2020-08-25 20:59 ` [PATCH 50/77] target/microblaze: Replace MSR_EE_FLAG with MSR_EE Richard Henderson
2020-08-25 20:59 ` [PATCH 51/77] target/microblaze: Cache mem_index in DisasContext Richard Henderson
2020-08-25 20:59 ` [PATCH 52/77] target/microblaze: Fix cpu unwind for stackprot Richard Henderson
2020-08-25 20:59 ` [PATCH 53/77] target/microblaze: Convert dec_load and dec_store to decodetree Richard Henderson
2020-08-25 20:59 ` [PATCH 54/77] target/microblaze: Assert no overlap in flags making up tb_flags Richard Henderson
2020-08-25 20:59 ` [PATCH 55/77] target/microblaze: Move bimm to BIMM_FLAG Richard Henderson
2020-08-25 20:59 ` [PATCH 56/77] target/microblaze: Store "current" iflags in insn_start Richard Henderson
2020-08-25 20:59 ` [PATCH 57/77] tcg: Add tcg_get_insn_start_param Richard Henderson
2020-08-25 20:59 ` [PATCH 58/77] target/microblaze: Use cc->do_unaligned_access Richard Henderson
2020-08-25 20:59 ` [PATCH 59/77] target/microblaze: Replace clear_imm with tb_flags_to_set Richard Henderson
2020-08-25 20:59 ` [PATCH 60/77] target/microblaze: Replace delayed_branch " Richard Henderson
2020-08-25 20:59 ` [PATCH 61/77] target/microblaze: Tidy mb_cpu_dump_state Richard Henderson
2020-08-25 20:59 ` [PATCH 62/77] target/microblaze: Try to keep imm and delay slot together Richard Henderson
2020-08-27 19:17 ` Edgar E. Iglesias
2020-08-27 21:33 ` Richard Henderson
2020-08-29 15:27 ` Richard Henderson
2020-08-25 20:59 ` [PATCH 63/77] target/microblaze: Convert brk and brki to decodetree Richard Henderson
2020-08-25 20:59 ` [PATCH 64/77] target/microblaze: Convert mbar " Richard Henderson
2020-08-27 9:24 ` Edgar E. Iglesias
2020-08-27 9:58 ` Richard Henderson
2020-08-27 10:08 ` Edgar E. Iglesias
2020-08-27 11:11 ` Richard Henderson
2020-08-25 20:59 ` [PATCH 65/77] target/microblaze: Reorganize branching Richard Henderson
2020-08-25 20:59 ` [PATCH 66/77] target/microblaze: Use tcg_gen_lookup_and_goto_ptr Richard Henderson
2020-08-28 6:33 ` Edgar E. Iglesias
2020-08-28 13:32 ` Richard Henderson
2020-08-25 20:59 ` [PATCH 67/77] target/microblaze: Convert dec_br to decodetree Richard Henderson
2020-08-25 20:59 ` [PATCH 68/77] target/microblaze: Convert dec_bcc " Richard Henderson
2020-08-25 20:59 ` [PATCH 69/77] target/microblaze: Convert dec_rts " Richard Henderson
2020-08-25 20:59 ` [PATCH 70/77] target/microblaze: Tidy do_rti, do_rtb, do_rte Richard Henderson
2020-08-25 20:59 ` [PATCH 71/77] target/microblaze: Convert msrclr, msrset to decodetree Richard Henderson
2020-08-25 20:59 ` [PATCH 72/77] target/microblaze: Convert dec_msr " Richard Henderson
2020-08-25 20:59 ` [PATCH 73/77] target/microblaze: Convert dec_stream " Richard Henderson
2020-08-27 21:10 ` Edgar E. Iglesias
2020-08-27 21:12 ` Richard Henderson
2020-08-25 20:59 ` [PATCH 74/77] target/microblaze: Remove last of old decoder Richard Henderson
2020-08-25 20:59 ` [PATCH 75/77] target/microblaze: Remove cpu_R[0] Richard Henderson
2020-08-25 20:59 ` [PATCH 76/77] target/microblaze: Add flags markup to some helpers Richard Henderson
2020-08-25 20:59 ` [PATCH 77/77] target/microblaze: Reduce linux-user address space to 32-bit Richard Henderson
2020-08-26 15:27 ` [PATCH 00/77] target/microblaze improvements Edgar E. Iglesias
2020-08-26 18:07 ` Edgar E. Iglesias
2020-08-27 9:11 ` Edgar E. Iglesias
2020-08-27 10:01 ` Richard Henderson
2020-08-27 10:22 ` Edgar E. Iglesias
2020-08-27 11:19 ` Richard Henderson
2020-08-27 17:09 ` Edgar E. Iglesias
2020-08-28 13:36 ` Richard Henderson
2020-08-28 14:04 ` Edgar E. Iglesias
2020-08-28 13:19 ` Edgar E. Iglesias
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